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<h1><a name="Message">Timing Messages</a></h1>
<table class="summary_table">
<tr>
<td class="label">Report Title</td>
<td>Timing Analysis Report</td>
</tr>
<tr>
<td class="label">Design File</td>
<td>D:\GaoYun_pro\gaoyun_cpu\GY_riscv\impl\gwsynthesis\GY_riscv.vg</td>
</tr>
<tr>
<td class="label">Physical Constraints File</td>
<td>D:\GaoYun_pro\gaoyun_cpu\GY_riscv\CST\PIN.cst</td>
</tr>
<tr>
<td class="label">Timing Constraint File</td>
<td>---</td>
</tr>
<tr>
<td class="label">Version</td>
<td>V1.9.8.06-1</td>
</tr>
<tr>
<td class="label">Part Number</td>
<td>GW1NR-LV9QN88PC6/I5</td>
</tr>
<tr>
<td class="label">Device</td>
<td>GW1NR-9C</td>
</tr>
<tr>
<td class="label">Created Time</td>
<td>Sat Nov 26 14:56:20 2022
</td>
</tr>
<tr>
<td class="label">Legal Announcement</td>
<td>Copyright (C)2014-2022 Gowin Semiconductor Corporation. All rights reserved.</td>
</tr>
</table>
<h1><a name="Summary">Timing Summaries</a></h1>
<h2><a name="STA_Tool_Run_Summary">STA Tool Run Summary:</a></h2>
<table class="summary_table">
<tr>
<td class="label">Setup Delay Model</td>
<td>Slow 1.14V 85C C6/I5</td>
</tr>
<tr>
<td class="label">Hold Delay Model</td>
<td>Fast 1.26V 0C C6/I5</td>
</tr>
<tr>
<td class="label">Numbers of Paths Analyzed</td>
<td>2374</td>
</tr>
<tr>
<td class="label">Numbers of Endpoints Analyzed</td>
<td>2241</td>
</tr>
<tr>
<td class="label">Numbers of Falling Endpoints</td>
<td>0</td>
</tr>
<tr>
<td class="label">Numbers of Setup Violated Endpoints</td>
<td>24</td>
</tr>
<tr>
<td class="label">Numbers of Hold Violated Endpoints</td>
<td>0</td>
</tr>
</table>
<h2><a name="Clock_Report">Clock Summary:</a></h2>
<table class="detail_table">
<tr>
<th class="label">Clock Name</th>
<th class="label">Type</th>
<th class="label">Period</th>
<th class="label">Frequency(MHz)</th>
<th class="label">Rise</th>
<th class="label">Fall</th>
<th class="label">Source</th>
<th class="label">Master</th>
<th class="label">Objects</th>
</tr>
<tr>
<td>clk</td>
<td>Base</td>
<td>20.000</td>
<td>50.000
<td>0.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td>clk_ibuf/I </td>
</tr>
</table>
<h2><a name="Max_Frequency_Report">Max Frequency Summary:</a></h2>
<table>
<tr>
<th>NO.</th>
<th>Clock Name</th>
<th>Constraint</th>
<th>Actual Fmax</th>
<th>Logic Level</th>
<th>Entity</th>
</tr>
<tr>
<td>1</td>
<td>clk</td>
<td>50.000(MHz)</td>
<td style="color: #FF0000;">48.446(MHz)</td>
<td>8</td>
<td>TOP</td>
</tr>
</table>
<h2><a name="Total_Negative_Slack_Report">Total Negative Slack Summary:</a></h2>
<table class="detail_table">
<tr>
<th class="label">Clock Name</th>
<th class="label">Analysis Type</th>
<th class="label">Endpoints TNS</th>
<th class="label">Number of Endpoints</th>
</tr>
<tr>
<td>clk</td>
<td>Setup</td>
<td>-5.956</td>
<td>24</td>
</tr>
<tr>
<td>clk</td>
<td>Hold</td>
<td>0.000</td>
<td>0</td>
</tr>
</table>
<h1><a name="Detail">Timing Details</a></h1>
<h2><a name="All_Path_Slack_Table">Path Slacks Table:</a></h2>
<h3><a name="Setup_Slack_Table">Setup Paths Table</a></h3>
<h4>Report Command:report_timing -setup -max_paths 25 -max_common_paths 1</h4>
<table class="detail_table">
<tr>
<th class="label">Path Number</th>
<th class="label">Path Slack</th>
<th class="label">From Node</th>
<th class="label">To Node</th>
<th class="label">From Clock</th>
<th class="label">To Clock</th>
<th class="label">Relation</th>
<th class="label">Clock Skew</th>
<th class="label">Data Delay</th>
</tr>
<tr style="color: #FF0000;">
<td>1</td>
<td>-0.642</td>
<td>picorv32_core/riscv32_alu_u1/instruction_reg_1_s0/Q</td>
<td>picorv32_core/riscv32_alu_u1/mret_reg_16_s0/D</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>20.000</td>
<td>0.000</td>
<td>20.242</td>
</tr>
<tr style="color: #FF0000;">
<td>2</td>
<td>-0.600</td>
<td>picorv32_core/riscv32_alu_u1/op1num_0_s0/Q</td>
<td>picorv32_core/riscv32_alu_u1/reg_wdata_5_s0/D</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>20.000</td>
<td>0.000</td>
<td>20.200</td>
</tr>
<tr style="color: #FF0000;">
<td>3</td>
<td>-0.580</td>
<td>picorv32_core/riscv32_alu_u1/op1num_1_s0/Q</td>
<td>picorv32_core/riscv32_alu_u1/risc_v_pc_1_s1/D</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>20.000</td>
<td>0.000</td>
<td>20.180</td>
</tr>
<tr style="color: #FF0000;">
<td>4</td>
<td>-0.393</td>
<td>picorv32_core/riscv32_alu_u1/op1num_1_s0/Q</td>
<td>picorv32_core/riscv32_alu_u1/risc_v_pc_13_s1/D</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>20.000</td>
<td>0.000</td>
<td>19.993</td>
</tr>
<tr style="color: #FF0000;">
<td>5</td>
<td>-0.380</td>
<td>picorv32_core/riscv32_alu_u1/op1num_5_s0/Q</td>
<td>picorv32_core/riscv32_alu_u1/reg_wdata_19_s0/D</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>20.000</td>
<td>0.000</td>
<td>19.980</td>
</tr>
<tr style="color: #FF0000;">
<td>6</td>
<td>-0.372</td>
<td>picorv32_core/riscv32_alu_u1/op1num_19_s0/Q</td>
<td>picorv32_core/riscv32_alu_u1/reg_wdata_21_s0/D</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>20.000</td>
<td>0.000</td>
<td>19.972</td>
</tr>
<tr style="color: #FF0000;">
<td>7</td>
<td>-0.323</td>
<td>picorv32_core/riscv32_alu_u1/reg_raddr_3_s3/Q</td>
<td>picorv32_core/riscv32_alu_u1/mem_wdata_11_s0/D</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>20.000</td>
<td>0.000</td>
<td>19.923</td>
</tr>
<tr style="color: #FF0000;">
<td>8</td>
<td>-0.323</td>
<td>picorv32_core/riscv32_alu_u1/reg_raddr_3_s3/Q</td>
<td>picorv32_core/riscv32_alu_u1/mem_wdata_19_s0/D</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>20.000</td>
<td>0.000</td>
<td>19.923</td>
</tr>
<tr style="color: #FF0000;">
<td>9</td>
<td>-0.279</td>
<td>picorv32_core/riscv32_alu_u1/op1num_2_s0/Q</td>
<td>picorv32_core/riscv32_alu_u1/reg_wdata_31_s0/D</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>20.000</td>
<td>0.000</td>
<td>19.879</td>
</tr>
<tr style="color: #FF0000;">
<td>10</td>
<td>-0.246</td>
<td>picorv32_core/riscv32_alu_u1/instruction_reg_14_s0/Q</td>
<td>picorv32_core/riscv32_alu_u1/reg_wdata_23_s0/D</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>20.000</td>
<td>0.000</td>
<td>19.846</td>
</tr>
<tr style="color: #FF0000;">
<td>11</td>
<td>-0.238</td>
<td>picorv32_core/riscv32_alu_u1/op1num_1_s0/Q</td>
<td>picorv32_core/riscv32_alu_u1/risc_v_pc_9_s1/D</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>20.000</td>
<td>0.000</td>
<td>19.838</td>
</tr>
<tr style="color: #FF0000;">
<td>12</td>
<td>-0.218</td>
<td>picorv32_core/riscv32_alu_u1/op1num_1_s0/Q</td>
<td>picorv32_core/riscv32_alu_u1/risc_v_pc_14_s1/D</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>20.000</td>
<td>0.000</td>
<td>19.818</td>
</tr>
<tr style="color: #FF0000;">
<td>13</td>
<td>-0.190</td>
<td>picorv32_core/riscv32_alu_u1/op1num_0_s0/Q</td>
<td>picorv32_core/riscv32_alu_u1/reg_wdata_11_s0/D</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>20.000</td>
<td>0.000</td>
<td>19.790</td>
</tr>
<tr style="color: #FF0000;">
<td>14</td>
<td>-0.143</td>
<td>picorv32_core/riscv32_alu_u1/op1num_0_s0/Q</td>
<td>picorv32_core/riscv32_alu_u1/reg_wdata_15_s0/D</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>20.000</td>
<td>0.000</td>
<td>19.743</td>
</tr>
<tr style="color: #FF0000;">
<td>15</td>
<td>-0.138</td>
<td>picorv32_core/riscv32_alu_u1/op1num_1_s0/Q</td>
<td>picorv32_core/riscv32_alu_u1/risc_v_pc_26_s1/D</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>20.000</td>
<td>0.000</td>
<td>19.738</td>
</tr>
<tr style="color: #FF0000;">
<td>16</td>
<td>-0.126</td>
<td>picorv32_core/riscv32_alu_u1/instruction_reg_14_s0/Q</td>
<td>picorv32_core/riscv32_alu_u1/reg_wdata_0_s0/D</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>20.000</td>
<td>0.000</td>
<td>19.726</td>
</tr>
<tr style="color: #FF0000;">
<td>17</td>
<td>-0.121</td>
<td>picorv32_core/riscv32_alu_u1/op1num_1_s0/Q</td>
<td>picorv32_core/riscv32_alu_u1/risc_v_pc_22_s1/D</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>20.000</td>
<td>0.000</td>
<td>19.721</td>
</tr>
<tr style="color: #FF0000;">
<td>18</td>
<td>-0.112</td>
<td>picorv32_core/riscv32_alu_u1/op1num_0_s0/Q</td>
<td>picorv32_core/riscv32_alu_u1/reg_wdata_10_s0/D</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>20.000</td>
<td>0.000</td>
<td>19.712</td>
</tr>
<tr style="color: #FF0000;">
<td>19</td>
<td>-0.110</td>
<td>picorv32_core/riscv32_alu_u1/instruction_reg_1_s0/Q</td>
<td>picorv32_core/riscv32_alu_u1/mret_reg_24_s0/D</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>20.000</td>
<td>0.000</td>
<td>19.710</td>
</tr>
<tr style="color: #FF0000;">
<td>20</td>
<td>-0.099</td>
<td>picorv32_core/riscv32_alu_u1/op1num_1_s0/Q</td>
<td>picorv32_core/riscv32_alu_u1/risc_v_pc_27_s1/D</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>20.000</td>
<td>0.000</td>
<td>19.699</td>
</tr>
<tr style="color: #FF0000;">
<td>21</td>
<td>-0.089</td>
<td>picorv32_core/riscv32_alu_u1/op1num_1_s0/Q</td>
<td>picorv32_core/riscv32_alu_u1/risc_v_pc_10_s1/D</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>20.000</td>
<td>0.000</td>
<td>19.689</td>
</tr>
<tr style="color: #FF0000;">
<td>22</td>
<td>-0.080</td>
<td>picorv32_core/riscv32_alu_u1/op1num_1_s0/Q</td>
<td>picorv32_core/riscv32_alu_u1/risc_v_pc_4_s1/D</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>20.000</td>
<td>0.000</td>
<td>19.680</td>
</tr>
<tr style="color: #FF0000;">
<td>23</td>
<td>-0.078</td>
<td>picorv32_core/riscv32_alu_u1/op1num_0_s0/Q</td>
<td>picorv32_core/riscv32_alu_u1/reg_wdata_24_s0/D</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>20.000</td>
<td>0.000</td>
<td>19.678</td>
</tr>
<tr style="color: #FF0000;">
<td>24</td>
<td>-0.076</td>
<td>picorv32_core/riscv32_alu_u1/op1num_0_s0/Q</td>
<td>picorv32_core/riscv32_alu_u1/reg_wdata_17_s0/D</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>20.000</td>
<td>0.000</td>
<td>19.676</td>
</tr>
<tr>
<td>25</td>
<td>0.004</td>
<td>picorv32_core/riscv32_alu_u1/op1num_1_s0/Q</td>
<td>picorv32_core/riscv32_alu_u1/cpu_state_0_s2/D</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>20.000</td>
<td>0.000</td>
<td>19.596</td>
</tr>
</table>
<h3><a name="Hold_Slack_Table">Hold Paths Table</a></h3>
<h4>Report Command:report_timing -hold -max_paths 25 -max_common_paths 1</h4>
<table class="detail_table">
<tr>
<th class="label">Path Number</th>
<th class="label">Path Slack</th>
<th class="label">From Node</th>
<th class="label">To Node</th>
<th class="label">From Clock</th>
<th class="label">To Clock</th>
<th class="label">Relation</th>
<th class="label">Clock Skew</th>
<th class="label">Data Delay</th>
</tr>
<tr>
<td>1</td>
<td>0.708</td>
<td>uart_memory_u1/uart_wdata_2_s1/Q</td>
<td>uart_memory_u1/uart_wdata_2_s1/D</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.708</td>
</tr>
<tr>
<td>2</td>
<td>0.708</td>
<td>uart_memory_u1/uart_delay_cnt_3_s0/Q</td>
<td>uart_memory_u1/uart_delay_cnt_3_s0/D</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.708</td>
</tr>
<tr>
<td>3</td>
<td>0.708</td>
<td>uart_memory_u1/uart_delay_cnt_14_s0/Q</td>
<td>uart_memory_u1/uart_delay_cnt_14_s0/D</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.708</td>
</tr>
<tr>
<td>4</td>
<td>0.708</td>
<td>picorv32_core/riscv32_alu_u1/cpu_state_0_s2/Q</td>
<td>picorv32_core/riscv32_alu_u1/cpu_state_0_s2/D</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.708</td>
</tr>
<tr>
<td>5</td>
<td>0.708</td>
<td>picorv32_core/riscv32_alu_u1/mret_reg_27_s0/Q</td>
<td>picorv32_core/riscv32_alu_u1/mret_reg_27_s0/D</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.708</td>
</tr>
<tr>
<td>6</td>
<td>0.708</td>
<td>picorv32_core/riscv32_alu_u1/mem_wstrb_0_s0/Q</td>
<td>picorv32_core/riscv32_alu_u1/mem_wstrb_0_s0/D</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.708</td>
</tr>
<tr>
<td>7</td>
<td>0.708</td>
<td>picorv32_core/riscv32_alu_u1/mem_wstrb_1_s0/Q</td>
<td>picorv32_core/riscv32_alu_u1/mem_wstrb_1_s0/D</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.708</td>
</tr>
<tr>
<td>8</td>
<td>0.708</td>
<td>picorv32_core/uart_debug_u1/u_uart_txd/state_0_s3/Q</td>
<td>picorv32_core/uart_debug_u1/u_uart_txd/state_0_s3/D</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.708</td>
</tr>
<tr>
<td>9</td>
<td>0.708</td>
<td>picorv32_core/uart_debug_u1/reset_out_s10/Q</td>
<td>picorv32_core/uart_debug_u1/reset_out_s10/D</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.708</td>
</tr>
<tr>
<td>10</td>
<td>0.708</td>
<td>picorv32_core/uart_debug_u1/uart_cnt_2_s0/Q</td>
<td>picorv32_core/uart_debug_u1/uart_cnt_2_s0/D</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.708</td>
</tr>
<tr>
<td>11</td>
<td>0.709</td>
<td>uart_memory_u1/u_uart_txd/cnt_clk_4_s0/Q</td>
<td>uart_memory_u1/u_uart_txd/cnt_clk_4_s0/D</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.709</td>
</tr>
<tr>
<td>12</td>
<td>0.709</td>
<td>uart_memory_u1/u_uart_recv/state_0_s3/Q</td>
<td>uart_memory_u1/u_uart_recv/state_0_s3/D</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.709</td>
</tr>
<tr>
<td>13</td>
<td>0.709</td>
<td>uart_memory_u1/u_uart_recv/state_2_s1/Q</td>
<td>uart_memory_u1/u_uart_recv/state_2_s1/D</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.709</td>
</tr>
<tr>
<td>14</td>
<td>0.709</td>
<td>uart_memory_u1/u_uart_recv/cnt_clk_0_s0/Q</td>
<td>uart_memory_u1/u_uart_recv/cnt_clk_0_s0/D</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.709</td>
</tr>
<tr>
<td>15</td>
<td>0.709</td>
<td>uart_memory_u1/u_uart_recv/cnt_clk_1_s0/Q</td>
<td>uart_memory_u1/u_uart_recv/cnt_clk_1_s0/D</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.709</td>
</tr>
<tr>
<td>16</td>
<td>0.709</td>
<td>uart_memory_u1/u_uart_recv/cnt_clk_4_s0/Q</td>
<td>uart_memory_u1/u_uart_recv/cnt_clk_4_s0/D</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.709</td>
</tr>
<tr>
<td>17</td>
<td>0.709</td>
<td>uart_memory_u1/uart_delay_cnt_0_s0/Q</td>
<td>uart_memory_u1/uart_delay_cnt_0_s0/D</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.709</td>
</tr>
<tr>
<td>18</td>
<td>0.709</td>
<td>uart_memory_u1/uart_delay_cnt_4_s0/Q</td>
<td>uart_memory_u1/uart_delay_cnt_4_s0/D</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.709</td>
</tr>
<tr>
<td>19</td>
<td>0.709</td>
<td>uart_memory_u1/uart_delay_cnt_6_s0/Q</td>
<td>uart_memory_u1/uart_delay_cnt_6_s0/D</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.709</td>
</tr>
<tr>
<td>20</td>
<td>0.709</td>
<td>uart_memory_u1/uart_delay_cnt_7_s0/Q</td>
<td>uart_memory_u1/uart_delay_cnt_7_s0/D</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.709</td>
</tr>
<tr>
<td>21</td>
<td>0.709</td>
<td>uart_memory_u1/uart_delay_cnt_9_s0/Q</td>
<td>uart_memory_u1/uart_delay_cnt_9_s0/D</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.709</td>
</tr>
<tr>
<td>22</td>
<td>0.709</td>
<td>uart_memory_u1/uart_delay_cnt_10_s0/Q</td>
<td>uart_memory_u1/uart_delay_cnt_10_s0/D</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.709</td>
</tr>
<tr>
<td>23</td>
<td>0.709</td>
<td>uart_memory_u1/uart_delay_cnt_11_s0/Q</td>
<td>uart_memory_u1/uart_delay_cnt_11_s0/D</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.709</td>
</tr>
<tr>
<td>24</td>
<td>0.709</td>
<td>picorv32_core/riscv32_alu_u1/mret_reg_18_s0/Q</td>
<td>picorv32_core/riscv32_alu_u1/mret_reg_18_s0/D</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.709</td>
</tr>
<tr>
<td>25</td>
<td>0.709</td>
<td>picorv32_core/riscv32_alu_u1/mret_reg_20_s0/Q</td>
<td>picorv32_core/riscv32_alu_u1/mret_reg_20_s0/D</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.709</td>
</tr>
</table>
<h3><a name="Recovery_Slack_Table">Recovery Paths Table</a></h3>
<h4>Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1</h4>
<table class="detail_table">
<tr>
<th class="label">Path Number</th>
<th class="label">Path Slack</th>
<th class="label">From Node</th>
<th class="label">To Node</th>
<th class="label">From Clock</th>
<th class="label">To Clock</th>
<th class="label">Relation</th>
<th class="label">Clock Skew</th>
<th class="label">Data Delay</th>
</tr>
<tr>
<td>1</td>
<td>16.368</td>
<td>picorv32_core/uart_debug_u1/reset_out_s10/Q</td>
<td>uart_memory_u1/u_uart_txd/state_1_s3/CLEAR</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>20.000</td>
<td>0.000</td>
<td>3.589</td>
</tr>
<tr>
<td>2</td>
<td>16.368</td>
<td>picorv32_core/uart_debug_u1/reset_out_s10/Q</td>
<td>uart_memory_u1/u_uart_txd/state_3_s10/CLEAR</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>20.000</td>
<td>0.000</td>
<td>3.589</td>
</tr>
<tr>
<td>3</td>
<td>16.368</td>
<td>picorv32_core/uart_debug_u1/reset_out_s10/Q</td>
<td>uart_memory_u1/u_uart_txd/state_0_s3/CLEAR</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>20.000</td>
<td>0.000</td>
<td>3.589</td>
</tr>
<tr>
<td>4</td>
<td>16.368</td>
<td>picorv32_core/uart_debug_u1/reset_out_s10/Q</td>
<td>uart_memory_u1/u_uart_txd/tx_flag_0_s8/CLEAR</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>20.000</td>
<td>0.000</td>
<td>3.589</td>
</tr>
<tr>
<td>5</td>
<td>16.368</td>
<td>picorv32_core/uart_debug_u1/reset_out_s10/Q</td>
<td>uart_memory_u1/u_uart_txd/uart_txd_0_s1/PRESET</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>20.000</td>
<td>0.000</td>
<td>3.589</td>
</tr>
<tr>
<td>6</td>
<td>16.368</td>
<td>picorv32_core/uart_debug_u1/reset_out_s10/Q</td>
<td>uart_memory_u1/u_uart_txd/state_2_s1/CLEAR</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>20.000</td>
<td>0.000</td>
<td>3.589</td>
</tr>
<tr>
<td>7</td>
<td>16.368</td>
<td>picorv32_core/uart_debug_u1/reset_out_s10/Q</td>
<td>uart_memory_u1/u_uart_txd/uart_data_0_0_s0/CLEAR</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>20.000</td>
<td>0.000</td>
<td>3.589</td>
</tr>
<tr>
<td>8</td>
<td>16.368</td>
<td>picorv32_core/uart_debug_u1/reset_out_s10/Q</td>
<td>uart_memory_u1/u_uart_txd/cnt_clk_0_s0/CLEAR</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>20.000</td>
<td>0.000</td>
<td>3.589</td>
</tr>
<tr>
<td>9</td>
<td>16.368</td>
<td>picorv32_core/uart_debug_u1/reset_out_s10/Q</td>
<td>uart_memory_u1/u_uart_txd/cnt_clk_1_s0/CLEAR</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>20.000</td>
<td>0.000</td>
<td>3.589</td>
</tr>
<tr>
<td>10</td>
<td>16.368</td>
<td>picorv32_core/uart_debug_u1/reset_out_s10/Q</td>
<td>uart_memory_u1/u_uart_txd/cnt_clk_2_s0/CLEAR</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>20.000</td>
<td>0.000</td>
<td>3.589</td>
</tr>
<tr>
<td>11</td>
<td>16.368</td>
<td>picorv32_core/uart_debug_u1/reset_out_s10/Q</td>
<td>uart_memory_u1/u_uart_txd/cnt_clk_3_s0/CLEAR</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>20.000</td>
<td>0.000</td>
<td>3.589</td>
</tr>
<tr>
<td>12</td>
<td>16.368</td>
<td>picorv32_core/uart_debug_u1/reset_out_s10/Q</td>
<td>uart_memory_u1/u_uart_txd/cnt_clk_4_s0/CLEAR</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>20.000</td>
<td>0.000</td>
<td>3.589</td>
</tr>
<tr>
<td>13</td>
<td>16.368</td>
<td>picorv32_core/uart_debug_u1/reset_out_s10/Q</td>
<td>uart_memory_u1/u_uart_txd/uart_data_1_0_s0/CLEAR</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>20.000</td>
<td>0.000</td>
<td>3.589</td>
</tr>
<tr>
<td>14</td>
<td>16.368</td>
<td>picorv32_core/uart_debug_u1/reset_out_s10/Q</td>
<td>uart_memory_u1/u_uart_recv/state_1_s3/CLEAR</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>20.000</td>
<td>0.000</td>
<td>3.589</td>
</tr>
<tr>
<td>15</td>
<td>16.368</td>
<td>picorv32_core/uart_debug_u1/reset_out_s10/Q</td>
<td>uart_memory_u1/u_uart_recv/state_3_s10/CLEAR</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>20.000</td>
<td>0.000</td>
<td>3.589</td>
</tr>
<tr>
<td>16</td>
<td>16.368</td>
<td>picorv32_core/uart_debug_u1/reset_out_s10/Q</td>
<td>uart_memory_u1/u_uart_recv/state_0_s3/CLEAR</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>20.000</td>
<td>0.000</td>
<td>3.589</td>
</tr>
<tr>
<td>17</td>
<td>16.368</td>
<td>picorv32_core/uart_debug_u1/reset_out_s10/Q</td>
<td>uart_memory_u1/u_uart_recv/uart_data_0_s1/CLEAR</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>20.000</td>
<td>0.000</td>
<td>3.589</td>
</tr>
<tr>
<td>18</td>
<td>16.368</td>
<td>picorv32_core/uart_debug_u1/reset_out_s10/Q</td>
<td>uart_memory_u1/u_uart_recv/uart_data_1_s1/CLEAR</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>20.000</td>
<td>0.000</td>
<td>3.589</td>
</tr>
<tr>
<td>19</td>
<td>16.368</td>
<td>picorv32_core/uart_debug_u1/reset_out_s10/Q</td>
<td>uart_memory_u1/u_uart_recv/uart_data_2_s1/CLEAR</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>20.000</td>
<td>0.000</td>
<td>3.589</td>
</tr>
<tr>
<td>20</td>
<td>16.368</td>
<td>picorv32_core/uart_debug_u1/reset_out_s10/Q</td>
<td>uart_memory_u1/u_uart_recv/uart_data_3_s1/CLEAR</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>20.000</td>
<td>0.000</td>
<td>3.589</td>
</tr>
<tr>
<td>21</td>
<td>16.368</td>
<td>picorv32_core/uart_debug_u1/reset_out_s10/Q</td>
<td>uart_memory_u1/u_uart_recv/uart_data_4_s1/CLEAR</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>20.000</td>
<td>0.000</td>
<td>3.589</td>
</tr>
<tr>
<td>22</td>
<td>16.368</td>
<td>picorv32_core/uart_debug_u1/reset_out_s10/Q</td>
<td>uart_memory_u1/u_uart_recv/uart_data_5_s1/CLEAR</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>20.000</td>
<td>0.000</td>
<td>3.589</td>
</tr>
<tr>
<td>23</td>
<td>16.368</td>
<td>picorv32_core/uart_debug_u1/reset_out_s10/Q</td>
<td>uart_memory_u1/u_uart_recv/uart_data_6_s1/CLEAR</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>20.000</td>
<td>0.000</td>
<td>3.589</td>
</tr>
<tr>
<td>24</td>
<td>16.368</td>
<td>picorv32_core/uart_debug_u1/reset_out_s10/Q</td>
<td>uart_memory_u1/u_uart_recv/uart_data_7_s1/CLEAR</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>20.000</td>
<td>0.000</td>
<td>3.589</td>
</tr>
<tr>
<td>25</td>
<td>16.368</td>
<td>picorv32_core/uart_debug_u1/reset_out_s10/Q</td>
<td>uart_memory_u1/u_uart_recv/state_2_s1/CLEAR</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>20.000</td>
<td>0.000</td>
<td>3.589</td>
</tr>
</table>
<h3><a name="Removal_Slack_Table">Removal Paths Table</a></h3>
<h4>Report Command:report_timing -removal -max_paths 25 -max_common_paths 1</h4>
<table class="detail_table">
<tr>
<th class="label">Path Number</th>
<th class="label">Path Slack</th>
<th class="label">From Node</th>
<th class="label">To Node</th>
<th class="label">From Clock</th>
<th class="label">To Clock</th>
<th class="label">Relation</th>
<th class="label">Clock Skew</th>
<th class="label">Data Delay</th>
</tr>
<tr>
<td>1</td>
<td>0.895</td>
<td>uart_memory_u1/overtime_oe_s0/Q</td>
<td>uart_memory_u1/overtime_0_s0/CLEAR</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.910</td>
</tr>
<tr>
<td>2</td>
<td>0.901</td>
<td>uart_memory_u1/overtime_oe_s0/Q</td>
<td>uart_memory_u1/overtime_6_s0/CLEAR</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.916</td>
</tr>
<tr>
<td>3</td>
<td>0.901</td>
<td>uart_memory_u1/overtime_oe_s0/Q</td>
<td>uart_memory_u1/overtime_7_s0/CLEAR</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.916</td>
</tr>
<tr>
<td>4</td>
<td>0.901</td>
<td>uart_memory_u1/overtime_oe_s0/Q</td>
<td>uart_memory_u1/overtime_8_s0/CLEAR</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.916</td>
</tr>
<tr>
<td>5</td>
<td>0.901</td>
<td>uart_memory_u1/overtime_oe_s0/Q</td>
<td>uart_memory_u1/overtime_9_s0/CLEAR</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.916</td>
</tr>
<tr>
<td>6</td>
<td>0.901</td>
<td>uart_memory_u1/overtime_oe_s0/Q</td>
<td>uart_memory_u1/overtime_10_s0/CLEAR</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.916</td>
</tr>
<tr>
<td>7</td>
<td>0.901</td>
<td>uart_memory_u1/overtime_oe_s0/Q</td>
<td>uart_memory_u1/overtime_11_s0/CLEAR</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.916</td>
</tr>
<tr>
<td>8</td>
<td>0.902</td>
<td>uart_memory_u1/overtime_oe_s0/Q</td>
<td>uart_memory_u1/overtime_1_s0/CLEAR</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.917</td>
</tr>
<tr>
<td>9</td>
<td>0.902</td>
<td>uart_memory_u1/overtime_oe_s0/Q</td>
<td>uart_memory_u1/overtime_2_s0/CLEAR</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.917</td>
</tr>
<tr>
<td>10</td>
<td>0.902</td>
<td>uart_memory_u1/overtime_oe_s0/Q</td>
<td>uart_memory_u1/overtime_3_s0/CLEAR</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.917</td>
</tr>
<tr>
<td>11</td>
<td>0.902</td>
<td>uart_memory_u1/overtime_oe_s0/Q</td>
<td>uart_memory_u1/overtime_4_s0/CLEAR</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.917</td>
</tr>
<tr>
<td>12</td>
<td>0.902</td>
<td>uart_memory_u1/overtime_oe_s0/Q</td>
<td>uart_memory_u1/overtime_5_s0/CLEAR</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.917</td>
</tr>
<tr>
<td>13</td>
<td>0.902</td>
<td>uart_memory_u1/overtime_oe_s0/Q</td>
<td>uart_memory_u1/overtime_12_s0/CLEAR</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.917</td>
</tr>
<tr>
<td>14</td>
<td>0.902</td>
<td>uart_memory_u1/overtime_oe_s0/Q</td>
<td>uart_memory_u1/overtime_13_s0/CLEAR</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.917</td>
</tr>
<tr>
<td>15</td>
<td>0.902</td>
<td>uart_memory_u1/overtime_oe_s0/Q</td>
<td>uart_memory_u1/overtime_14_s0/CLEAR</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.917</td>
</tr>
<tr>
<td>16</td>
<td>0.902</td>
<td>uart_memory_u1/overtime_oe_s0/Q</td>
<td>uart_memory_u1/overtime_15_s0/CLEAR</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.917</td>
</tr>
<tr>
<td>17</td>
<td>0.902</td>
<td>uart_memory_u1/overtime_oe_s0/Q</td>
<td>uart_memory_u1/overtime_16_s0/CLEAR</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.917</td>
</tr>
<tr>
<td>18</td>
<td>0.902</td>
<td>uart_memory_u1/overtime_oe_s0/Q</td>
<td>uart_memory_u1/overtime_17_s0/CLEAR</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.917</td>
</tr>
<tr>
<td>19</td>
<td>0.902</td>
<td>uart_memory_u1/overtime_oe_s0/Q</td>
<td>uart_memory_u1/overtime_18_s0/CLEAR</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.917</td>
</tr>
<tr>
<td>20</td>
<td>0.902</td>
<td>uart_memory_u1/overtime_oe_s0/Q</td>
<td>uart_memory_u1/overtime_19_s0/CLEAR</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.917</td>
</tr>
<tr>
<td>21</td>
<td>0.902</td>
<td>uart_memory_u1/overtime_oe_s0/Q</td>
<td>uart_memory_u1/overtime_20_s0/CLEAR</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.917</td>
</tr>
<tr>
<td>22</td>
<td>0.902</td>
<td>uart_memory_u1/overtime_oe_s0/Q</td>
<td>uart_memory_u1/overtime_21_s0/CLEAR</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.917</td>
</tr>
<tr>
<td>23</td>
<td>0.902</td>
<td>uart_memory_u1/overtime_oe_s0/Q</td>
<td>uart_memory_u1/overtime_22_s0/CLEAR</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.917</td>
</tr>
<tr>
<td>24</td>
<td>0.902</td>
<td>uart_memory_u1/overtime_oe_s0/Q</td>
<td>uart_memory_u1/overtime_23_s0/CLEAR</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.917</td>
</tr>
<tr>
<td>25</td>
<td>1.161</td>
<td>uart_memory_u1/overtime_oe_s0/Q</td>
<td>uart_memory_u1/overtime_24_s0/CLEAR</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>1.176</td>
</tr>
</table>
<h2><a name="MIN_PULSE_WIDTH_TABLE">Minimum Pulse Width Table:</a></h2>
<table class="detail_table">
<tr>
<th class="label">Number</th>
<th class="label">Slack</th>
<th class="label">Actual Width</th>
<th class="label">Required Width</th>
<th class="label">Type</th>
<th class="label">Clock</th>
<th class="label">Objects</th>
</tr>
<h4>Report Command:report_min_pulse_width -nworst 10 -detail</h4>
<tr>
<td>1</td>
<td>8.532</td>
<td>9.782</td>
<td>1.250</td>
<td>Low Pulse Width</td>
<td>clk</td>
<td>out_byte_7_s2</td>
</tr>
<tr>
<td>2</td>
<td>8.532</td>
<td>9.782</td>
<td>1.250</td>
<td>Low Pulse Width</td>
<td>clk</td>
<td>out_byte_5_s1</td>
</tr>
<tr>
<td>3</td>
<td>8.532</td>
<td>9.782</td>
<td>1.250</td>
<td>Low Pulse Width</td>
<td>clk</td>
<td>out_byte_1_s1</td>
</tr>
<tr>
<td>4</td>
<td>8.532</td>
<td>9.782</td>
<td>1.250</td>
<td>Low Pulse Width</td>
<td>clk</td>
<td>mem_rdata_r0_25_s0</td>
</tr>
<tr>
<td>5</td>
<td>8.532</td>
<td>9.782</td>
<td>1.250</td>
<td>Low Pulse Width</td>
<td>clk</td>
<td>mem_rdata_r0_9_s0</td>
</tr>
<tr>
<td>6</td>
<td>8.532</td>
<td>9.782</td>
<td>1.250</td>
<td>Low Pulse Width</td>
<td>clk</td>
<td>picorv32_core/timer_cnt_12_s0</td>
</tr>
<tr>
<td>7</td>
<td>8.532</td>
<td>9.782</td>
<td>1.250</td>
<td>Low Pulse Width</td>
<td>clk</td>
<td>picorv32_core/pcpi_rd_12_s0</td>
</tr>
<tr>
<td>8</td>
<td>8.532</td>
<td>9.782</td>
<td>1.250</td>
<td>Low Pulse Width</td>
<td>clk</td>
<td>picorv32_core/riscv32_alu_u1/irq_reg_15_s0</td>
</tr>
<tr>
<td>9</td>
<td>8.532</td>
<td>9.782</td>
<td>1.250</td>
<td>Low Pulse Width</td>
<td>clk</td>
<td>picorv32_core/riscv32_alu_u1/op2num_17_s0</td>
</tr>
<tr>
<td>10</td>
<td>8.532</td>
<td>9.782</td>
<td>1.250</td>
<td>Low Pulse Width</td>
<td>clk</td>
<td>picorv32_core/riscv32_alu_u1/op2num_18_s0</td>
</tr>
</table>
<h2><a name="Timing_Report_by_Analysis_Type">Timing Report By Analysis Type:</a></h2>
<h3><a name="Setup_Analysis">Setup Analysis Report</a></h3>
<h4>Report Command:report_timing -setup -max_paths 25 -max_common_paths 1</h4>
<h3>Path1</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-0.642</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>21.468</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>20.826</td>
</tr>
<tr>
<td class="label">From</td>
<td>picorv32_core/riscv32_alu_u1/instruction_reg_1_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>picorv32_core/riscv32_alu_u1/mret_reg_16_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>865</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.226</td>
<td>0.244</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R14C18[1][B]</td>
<td>picorv32_core/riscv32_alu_u1/instruction_reg_1_s0/CLK</td>
</tr>
<tr>
<td>1.684</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>5</td>
<td>R14C18[1][B]</td>
<td style=" font-weight:bold;">picorv32_core/riscv32_alu_u1/instruction_reg_1_s0/Q</td>
</tr>
<tr>
<td>3.794</td>
<td>2.109</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R23C28[3][A]</td>
<td>picorv32_core/riscv32_alu_u1/reg_waddr_4_s4/I3</td>
</tr>
<tr>
<td>4.616</td>
<td>0.822</td>
<td>tINS</td>
<td>FF</td>
<td>22</td>
<td>R23C28[3][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/reg_waddr_4_s4/F</td>
</tr>
<tr>
<td>5.965</td>
<td>1.349</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R21C31[3][A]</td>
<td>picorv32_core/riscv32_alu_u1/irq_reg_29_s9/I3</td>
</tr>
<tr>
<td>6.591</td>
<td>0.626</td>
<td>tINS</td>
<td>FF</td>
<td>14</td>
<td>R21C31[3][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/irq_reg_29_s9/F</td>
</tr>
<tr>
<td>8.392</td>
<td>1.801</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R16C32[1][B]</td>
<td>picorv32_core/riscv32_alu_u1/irq_reg_29_s10/I3</td>
</tr>
<tr>
<td>9.018</td>
<td>0.626</td>
<td>tINS</td>
<td>FF</td>
<td>16</td>
<td>R16C32[1][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/irq_reg_29_s10/F</td>
</tr>
<tr>
<td>10.994</td>
<td>1.976</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R7C23[2][A]</td>
<td>picorv32_core/riscv32_alu_u1/n6954_s14/I2</td>
</tr>
<tr>
<td>12.093</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>23</td>
<td>R7C23[2][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n6954_s14/F</td>
</tr>
<tr>
<td>14.588</td>
<td>2.495</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R11C40[2][A]</td>
<td>picorv32_core/riscv32_alu_u1/n6820_s15/I0</td>
</tr>
<tr>
<td>15.410</td>
<td>0.822</td>
<td>tINS</td>
<td>FF</td>
<td>17</td>
<td>R11C40[2][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n6820_s15/F</td>
</tr>
<tr>
<td>17.715</td>
<td>2.306</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R13C22[1][B]</td>
<td>picorv32_core/riscv32_alu_u1/n6792_s15/I1</td>
</tr>
<tr>
<td>18.537</td>
<td>0.822</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R13C22[1][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n6792_s15/F</td>
</tr>
<tr>
<td>20.646</td>
<td>2.108</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R13C35[0][A]</td>
<td>picorv32_core/riscv32_alu_u1/n6792_s12/I3</td>
</tr>
<tr>
<td>21.468</td>
<td>0.822</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R13C35[0][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n6792_s12/F</td>
</tr>
<tr>
<td>21.468</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R13C35[0][A]</td>
<td style=" font-weight:bold;">picorv32_core/riscv32_alu_u1/mret_reg_16_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>20.000</td>
<td>20.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>20.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>865</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>21.226</td>
<td>0.244</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C35[0][A]</td>
<td>picorv32_core/riscv32_alu_u1/mret_reg_16_s0/CLK</td>
</tr>
<tr>
<td>20.826</td>
<td>-0.400</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R13C35[0][A]</td>
<td>picorv32_core/riscv32_alu_u1/mret_reg_16_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>20.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>8</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.982, 80.100%; route: 0.244, 19.900%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 5.639, 27.858%; route: 14.144, 69.877%; tC2Q: 0.458, 2.264%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.982, 80.100%; route: 0.244, 19.900%</td>
</tr>
</table>
<h3>Path2</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-0.600</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>21.426</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>20.826</td>
</tr>
<tr>
<td class="label">From</td>
<td>picorv32_core/riscv32_alu_u1/op1num_0_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>picorv32_core/riscv32_alu_u1/reg_wdata_5_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>865</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.226</td>
<td>0.244</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R25C17[1][B]</td>
<td>picorv32_core/riscv32_alu_u1/op1num_0_s0/CLK</td>
</tr>
<tr>
<td>1.684</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>11</td>
<td>R25C17[1][B]</td>
<td style=" font-weight:bold;">picorv32_core/riscv32_alu_u1/op1num_0_s0/Q</td>
</tr>
<tr>
<td>4.942</td>
<td>3.258</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R16C40[0][A]</td>
<td>picorv32_core/riscv32_alu_u1/op1_add_op2_res_0_s/I0</td>
</tr>
<tr>
<td>5.987</td>
<td>1.045</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R16C40[0][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/op1_add_op2_res_0_s/COUT</td>
</tr>
<tr>
<td>5.987</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R16C40[0][B]</td>
<td>picorv32_core/riscv32_alu_u1/op1_add_op2_res_1_s/CIN</td>
</tr>
<tr>
<td>6.550</td>
<td>0.563</td>
<td>tINS</td>
<td>FF</td>
<td>20</td>
<td>R16C40[0][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/op1_add_op2_res_1_s/SUM</td>
</tr>
<tr>
<td>8.352</td>
<td>1.802</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R15C29[2][B]</td>
<td>picorv32_core/riscv32_alu_u1/n5972_s53/I0</td>
</tr>
<tr>
<td>9.384</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>8</td>
<td>R15C29[2][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n5972_s53/F</td>
</tr>
<tr>
<td>12.649</td>
<td>3.265</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C13[3][A]</td>
<td>picorv32_core/riscv32_alu_u1/n5976_s57/I2</td>
</tr>
<tr>
<td>13.748</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R18C13[3][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n5976_s57/F</td>
</tr>
<tr>
<td>15.521</td>
<td>1.773</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R17C18[1][A]</td>
<td>picorv32_core/riscv32_alu_u1/n5976_s46/I2</td>
</tr>
<tr>
<td>16.147</td>
<td>0.626</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R17C18[1][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n5976_s46/F</td>
</tr>
<tr>
<td>18.266</td>
<td>2.119</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R17C32[0][A]</td>
<td>picorv32_core/riscv32_alu_u1/n5976_s36/I0</td>
</tr>
<tr>
<td>19.298</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R17C32[0][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n5976_s36/F</td>
</tr>
<tr>
<td>20.604</td>
<td>1.305</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R17C36[0][A]</td>
<td>picorv32_core/riscv32_alu_u1/n5976_s33/I2</td>
</tr>
<tr>
<td>21.426</td>
<td>0.822</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R17C36[0][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n5976_s33/F</td>
</tr>
<tr>
<td>21.426</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R17C36[0][A]</td>
<td style=" font-weight:bold;">picorv32_core/riscv32_alu_u1/reg_wdata_5_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>20.000</td>
<td>20.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>20.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>865</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>21.226</td>
<td>0.244</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C36[0][A]</td>
<td>picorv32_core/riscv32_alu_u1/reg_wdata_5_s0/CLK</td>
</tr>
<tr>
<td>20.826</td>
<td>-0.400</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R17C36[0][A]</td>
<td>picorv32_core/riscv32_alu_u1/reg_wdata_5_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>20.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>8</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.982, 80.100%; route: 0.244, 19.900%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 6.219, 30.787%; route: 13.523, 66.944%; tC2Q: 0.458, 2.269%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.982, 80.100%; route: 0.244, 19.900%</td>
</tr>
</table>
<h3>Path3</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-0.580</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>21.406</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>20.826</td>
</tr>
<tr>
<td class="label">From</td>
<td>picorv32_core/riscv32_alu_u1/op1num_1_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>picorv32_core/riscv32_alu_u1/risc_v_pc_1_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>865</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.226</td>
<td>0.244</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R14C15[0][A]</td>
<td>picorv32_core/riscv32_alu_u1/op1num_1_s0/CLK</td>
</tr>
<tr>
<td>1.684</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>12</td>
<td>R14C15[0][A]</td>
<td style=" font-weight:bold;">picorv32_core/riscv32_alu_u1/op1num_1_s0/Q</td>
</tr>
<tr>
<td>4.478</td>
<td>2.793</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C31[1][A]</td>
<td>picorv32_core/riscv32_alu_u1/n246_s64/I0</td>
</tr>
<tr>
<td>5.436</td>
<td>0.958</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C31[1][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n246_s64/COUT</td>
</tr>
<tr>
<td>5.436</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C31[1][B]</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s65/CIN</td>
</tr>
<tr>
<td>5.493</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C31[1][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s65/COUT</td>
</tr>
<tr>
<td>5.493</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C31[2][A]</td>
<td>picorv32_core/riscv32_alu_u1/n246_s65/CIN</td>
</tr>
<tr>
<td>5.550</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C31[2][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n246_s65/COUT</td>
</tr>
<tr>
<td>5.550</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C31[2][B]</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s66/CIN</td>
</tr>
<tr>
<td>5.607</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C31[2][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s66/COUT</td>
</tr>
<tr>
<td>5.607</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C32[0][A]</td>
<td>picorv32_core/riscv32_alu_u1/n246_s66/CIN</td>
</tr>
<tr>
<td>5.664</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C32[0][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n246_s66/COUT</td>
</tr>
<tr>
<td>5.664</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C32[0][B]</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s67/CIN</td>
</tr>
<tr>
<td>5.721</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C32[0][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s67/COUT</td>
</tr>
<tr>
<td>5.721</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C32[1][A]</td>
<td>picorv32_core/riscv32_alu_u1/n246_s67/CIN</td>
</tr>
<tr>
<td>5.778</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C32[1][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n246_s67/COUT</td>
</tr>
<tr>
<td>5.778</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C32[1][B]</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s68/CIN</td>
</tr>
<tr>
<td>5.835</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C32[1][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s68/COUT</td>
</tr>
<tr>
<td>5.835</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C32[2][A]</td>
<td>picorv32_core/riscv32_alu_u1/n246_s68/CIN</td>
</tr>
<tr>
<td>5.892</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C32[2][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n246_s68/COUT</td>
</tr>
<tr>
<td>5.892</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C32[2][B]</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s69/CIN</td>
</tr>
<tr>
<td>5.949</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C32[2][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s69/COUT</td>
</tr>
<tr>
<td>5.949</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C33[0][A]</td>
<td>picorv32_core/riscv32_alu_u1/n246_s69/CIN</td>
</tr>
<tr>
<td>6.006</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C33[0][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n246_s69/COUT</td>
</tr>
<tr>
<td>6.006</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C33[0][B]</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s70/CIN</td>
</tr>
<tr>
<td>6.063</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C33[0][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s70/COUT</td>
</tr>
<tr>
<td>6.063</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C33[1][A]</td>
<td>picorv32_core/riscv32_alu_u1/n246_s70/CIN</td>
</tr>
<tr>
<td>6.120</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C33[1][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n246_s70/COUT</td>
</tr>
<tr>
<td>6.120</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C33[1][B]</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s71/CIN</td>
</tr>
<tr>
<td>6.177</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C33[1][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s71/COUT</td>
</tr>
<tr>
<td>6.177</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C33[2][A]</td>
<td>picorv32_core/riscv32_alu_u1/n246_s71/CIN</td>
</tr>
<tr>
<td>6.234</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C33[2][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n246_s71/COUT</td>
</tr>
<tr>
<td>6.234</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C33[2][B]</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s72/CIN</td>
</tr>
<tr>
<td>6.291</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C33[2][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s72/COUT</td>
</tr>
<tr>
<td>6.291</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C34[0][A]</td>
<td>picorv32_core/riscv32_alu_u1/n246_s72/CIN</td>
</tr>
<tr>
<td>6.348</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C34[0][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n246_s72/COUT</td>
</tr>
<tr>
<td>6.348</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C34[0][B]</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s73/CIN</td>
</tr>
<tr>
<td>6.405</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C34[0][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s73/COUT</td>
</tr>
<tr>
<td>6.405</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C34[1][A]</td>
<td>picorv32_core/riscv32_alu_u1/n246_s73/CIN</td>
</tr>
<tr>
<td>6.462</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C34[1][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n246_s73/COUT</td>
</tr>
<tr>
<td>6.462</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C34[1][B]</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s74/CIN</td>
</tr>
<tr>
<td>6.519</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C34[1][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s74/COUT</td>
</tr>
<tr>
<td>6.519</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C34[2][A]</td>
<td>picorv32_core/riscv32_alu_u1/n246_s74/CIN</td>
</tr>
<tr>
<td>6.576</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C34[2][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n246_s74/COUT</td>
</tr>
<tr>
<td>6.576</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C34[2][B]</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s75/CIN</td>
</tr>
<tr>
<td>6.633</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C34[2][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s75/COUT</td>
</tr>
<tr>
<td>6.633</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C35[0][A]</td>
<td>picorv32_core/riscv32_alu_u1/n246_s75/CIN</td>
</tr>
<tr>
<td>6.690</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C35[0][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n246_s75/COUT</td>
</tr>
<tr>
<td>6.690</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C35[0][B]</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s76/CIN</td>
</tr>
<tr>
<td>6.747</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C35[0][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s76/COUT</td>
</tr>
<tr>
<td>6.747</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C35[1][A]</td>
<td>picorv32_core/riscv32_alu_u1/n246_s76/CIN</td>
</tr>
<tr>
<td>6.804</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C35[1][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n246_s76/COUT</td>
</tr>
<tr>
<td>6.804</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C35[1][B]</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s77/CIN</td>
</tr>
<tr>
<td>6.861</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C35[1][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s77/COUT</td>
</tr>
<tr>
<td>6.861</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C35[2][A]</td>
<td>picorv32_core/riscv32_alu_u1/n246_s77/CIN</td>
</tr>
<tr>
<td>6.918</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C35[2][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n246_s77/COUT</td>
</tr>
<tr>
<td>6.918</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C35[2][B]</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s78/CIN</td>
</tr>
<tr>
<td>6.975</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C35[2][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s78/COUT</td>
</tr>
<tr>
<td>6.975</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C36[0][A]</td>
<td>picorv32_core/riscv32_alu_u1/n246_s78/CIN</td>
</tr>
<tr>
<td>7.032</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C36[0][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n246_s78/COUT</td>
</tr>
<tr>
<td>8.569</td>
<td>1.538</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R22C34[3][B]</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s80/I2</td>
</tr>
<tr>
<td>9.601</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>R22C34[3][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s80/F</td>
</tr>
<tr>
<td>10.416</td>
<td>0.814</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R21C32[3][B]</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_unsigned_s1/I2</td>
</tr>
<tr>
<td>11.515</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>R21C32[3][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/op1_ge_op2_unsigned_s1/F</td>
</tr>
<tr>
<td>11.526</td>
<td>0.011</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R21C32[0][B]</td>
<td>picorv32_core/riscv32_alu_u1/n1673_s10/I3</td>
</tr>
<tr>
<td>12.558</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R21C32[0][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n1673_s10/F</td>
</tr>
<tr>
<td>12.563</td>
<td>0.005</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R21C32[1][B]</td>
<td>picorv32_core/riscv32_alu_u1/n6826_s22/I0</td>
</tr>
<tr>
<td>13.624</td>
<td>1.061</td>
<td>tINS</td>
<td>FR</td>
<td>2</td>
<td>R21C32[1][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n6826_s22/F</td>
</tr>
<tr>
<td>14.045</td>
<td>0.421</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C31[1][A]</td>
<td>picorv32_core/riscv32_alu_u1/n6826_s17/I0</td>
</tr>
<tr>
<td>14.867</td>
<td>0.822</td>
<td>tINS</td>
<td>RF</td>
<td>2</td>
<td>R21C31[1][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n6826_s17/F</td>
</tr>
<tr>
<td>14.878</td>
<td>0.011</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R21C31[2][B]</td>
<td>picorv32_core/riscv32_alu_u1/n6826_s12/I2</td>
</tr>
<tr>
<td>15.504</td>
<td>0.626</td>
<td>tINS</td>
<td>FF</td>
<td>17</td>
<td>R21C31[2][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n6826_s12/F</td>
</tr>
<tr>
<td>18.609</td>
<td>3.105</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R15C18[3][A]</td>
<td>picorv32_core/riscv32_alu_u1/n6886_s8/I0</td>
</tr>
<tr>
<td>19.641</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R15C18[3][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n6886_s8/F</td>
</tr>
<tr>
<td>20.780</td>
<td>1.139</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R16C14[2][B]</td>
<td>picorv32_core/riscv32_alu_u1/n6886_s12/I0</td>
</tr>
<tr>
<td>21.406</td>
<td>0.626</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R16C14[2][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n6886_s12/F</td>
</tr>
<tr>
<td>21.406</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R16C14[2][B]</td>
<td style=" font-weight:bold;">picorv32_core/riscv32_alu_u1/risc_v_pc_1_s1/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>20.000</td>
<td>20.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>20.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>865</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>21.226</td>
<td>0.244</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R16C14[2][B]</td>
<td>picorv32_core/riscv32_alu_u1/risc_v_pc_1_s1/CLK</td>
</tr>
<tr>
<td>20.826</td>
<td>-0.400</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R16C14[2][B]</td>
<td>picorv32_core/riscv32_alu_u1/risc_v_pc_1_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>20.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>14</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.982, 80.100%; route: 0.244, 19.900%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 9.884, 48.978%; route: 9.838, 48.751%; tC2Q: 0.458, 2.271%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.982, 80.100%; route: 0.244, 19.900%</td>
</tr>
</table>
<h3>Path4</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-0.393</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>21.219</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>20.826</td>
</tr>
<tr>
<td class="label">From</td>
<td>picorv32_core/riscv32_alu_u1/op1num_1_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>picorv32_core/riscv32_alu_u1/risc_v_pc_13_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>865</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.226</td>
<td>0.244</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R14C15[0][A]</td>
<td>picorv32_core/riscv32_alu_u1/op1num_1_s0/CLK</td>
</tr>
<tr>
<td>1.684</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>12</td>
<td>R14C15[0][A]</td>
<td style=" font-weight:bold;">picorv32_core/riscv32_alu_u1/op1num_1_s0/Q</td>
</tr>
<tr>
<td>4.478</td>
<td>2.793</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C31[1][A]</td>
<td>picorv32_core/riscv32_alu_u1/n246_s64/I0</td>
</tr>
<tr>
<td>5.436</td>
<td>0.958</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C31[1][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n246_s64/COUT</td>
</tr>
<tr>
<td>5.436</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C31[1][B]</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s65/CIN</td>
</tr>
<tr>
<td>5.493</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C31[1][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s65/COUT</td>
</tr>
<tr>
<td>5.493</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C31[2][A]</td>
<td>picorv32_core/riscv32_alu_u1/n246_s65/CIN</td>
</tr>
<tr>
<td>5.550</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C31[2][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n246_s65/COUT</td>
</tr>
<tr>
<td>5.550</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C31[2][B]</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s66/CIN</td>
</tr>
<tr>
<td>5.607</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C31[2][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s66/COUT</td>
</tr>
<tr>
<td>5.607</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C32[0][A]</td>
<td>picorv32_core/riscv32_alu_u1/n246_s66/CIN</td>
</tr>
<tr>
<td>5.664</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C32[0][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n246_s66/COUT</td>
</tr>
<tr>
<td>5.664</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C32[0][B]</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s67/CIN</td>
</tr>
<tr>
<td>5.721</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C32[0][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s67/COUT</td>
</tr>
<tr>
<td>5.721</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C32[1][A]</td>
<td>picorv32_core/riscv32_alu_u1/n246_s67/CIN</td>
</tr>
<tr>
<td>5.778</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C32[1][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n246_s67/COUT</td>
</tr>
<tr>
<td>5.778</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C32[1][B]</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s68/CIN</td>
</tr>
<tr>
<td>5.835</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C32[1][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s68/COUT</td>
</tr>
<tr>
<td>5.835</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C32[2][A]</td>
<td>picorv32_core/riscv32_alu_u1/n246_s68/CIN</td>
</tr>
<tr>
<td>5.892</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C32[2][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n246_s68/COUT</td>
</tr>
<tr>
<td>5.892</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C32[2][B]</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s69/CIN</td>
</tr>
<tr>
<td>5.949</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C32[2][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s69/COUT</td>
</tr>
<tr>
<td>5.949</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C33[0][A]</td>
<td>picorv32_core/riscv32_alu_u1/n246_s69/CIN</td>
</tr>
<tr>
<td>6.006</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C33[0][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n246_s69/COUT</td>
</tr>
<tr>
<td>6.006</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C33[0][B]</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s70/CIN</td>
</tr>
<tr>
<td>6.063</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C33[0][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s70/COUT</td>
</tr>
<tr>
<td>6.063</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C33[1][A]</td>
<td>picorv32_core/riscv32_alu_u1/n246_s70/CIN</td>
</tr>
<tr>
<td>6.120</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C33[1][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n246_s70/COUT</td>
</tr>
<tr>
<td>6.120</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C33[1][B]</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s71/CIN</td>
</tr>
<tr>
<td>6.177</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C33[1][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s71/COUT</td>
</tr>
<tr>
<td>6.177</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C33[2][A]</td>
<td>picorv32_core/riscv32_alu_u1/n246_s71/CIN</td>
</tr>
<tr>
<td>6.234</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C33[2][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n246_s71/COUT</td>
</tr>
<tr>
<td>6.234</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C33[2][B]</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s72/CIN</td>
</tr>
<tr>
<td>6.291</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C33[2][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s72/COUT</td>
</tr>
<tr>
<td>6.291</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C34[0][A]</td>
<td>picorv32_core/riscv32_alu_u1/n246_s72/CIN</td>
</tr>
<tr>
<td>6.348</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C34[0][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n246_s72/COUT</td>
</tr>
<tr>
<td>6.348</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C34[0][B]</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s73/CIN</td>
</tr>
<tr>
<td>6.405</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C34[0][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s73/COUT</td>
</tr>
<tr>
<td>6.405</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C34[1][A]</td>
<td>picorv32_core/riscv32_alu_u1/n246_s73/CIN</td>
</tr>
<tr>
<td>6.462</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C34[1][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n246_s73/COUT</td>
</tr>
<tr>
<td>6.462</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C34[1][B]</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s74/CIN</td>
</tr>
<tr>
<td>6.519</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C34[1][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s74/COUT</td>
</tr>
<tr>
<td>6.519</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C34[2][A]</td>
<td>picorv32_core/riscv32_alu_u1/n246_s74/CIN</td>
</tr>
<tr>
<td>6.576</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C34[2][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n246_s74/COUT</td>
</tr>
<tr>
<td>6.576</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C34[2][B]</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s75/CIN</td>
</tr>
<tr>
<td>6.633</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C34[2][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s75/COUT</td>
</tr>
<tr>
<td>6.633</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C35[0][A]</td>
<td>picorv32_core/riscv32_alu_u1/n246_s75/CIN</td>
</tr>
<tr>
<td>6.690</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C35[0][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n246_s75/COUT</td>
</tr>
<tr>
<td>6.690</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C35[0][B]</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s76/CIN</td>
</tr>
<tr>
<td>6.747</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C35[0][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s76/COUT</td>
</tr>
<tr>
<td>6.747</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C35[1][A]</td>
<td>picorv32_core/riscv32_alu_u1/n246_s76/CIN</td>
</tr>
<tr>
<td>6.804</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C35[1][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n246_s76/COUT</td>
</tr>
<tr>
<td>6.804</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C35[1][B]</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s77/CIN</td>
</tr>
<tr>
<td>6.861</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C35[1][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s77/COUT</td>
</tr>
<tr>
<td>6.861</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C35[2][A]</td>
<td>picorv32_core/riscv32_alu_u1/n246_s77/CIN</td>
</tr>
<tr>
<td>6.918</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C35[2][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n246_s77/COUT</td>
</tr>
<tr>
<td>6.918</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C35[2][B]</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s78/CIN</td>
</tr>
<tr>
<td>6.975</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C35[2][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s78/COUT</td>
</tr>
<tr>
<td>6.975</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C36[0][A]</td>
<td>picorv32_core/riscv32_alu_u1/n246_s78/CIN</td>
</tr>
<tr>
<td>7.032</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C36[0][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n246_s78/COUT</td>
</tr>
<tr>
<td>8.569</td>
<td>1.538</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R22C34[3][B]</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s80/I2</td>
</tr>
<tr>
<td>9.601</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>R22C34[3][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s80/F</td>
</tr>
<tr>
<td>10.416</td>
<td>0.814</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R21C32[3][B]</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_unsigned_s1/I2</td>
</tr>
<tr>
<td>11.515</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>R21C32[3][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/op1_ge_op2_unsigned_s1/F</td>
</tr>
<tr>
<td>11.526</td>
<td>0.011</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R21C32[0][B]</td>
<td>picorv32_core/riscv32_alu_u1/n1673_s10/I3</td>
</tr>
<tr>
<td>12.558</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R21C32[0][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n1673_s10/F</td>
</tr>
<tr>
<td>12.563</td>
<td>0.005</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R21C32[1][B]</td>
<td>picorv32_core/riscv32_alu_u1/n6826_s22/I0</td>
</tr>
<tr>
<td>13.624</td>
<td>1.061</td>
<td>tINS</td>
<td>FR</td>
<td>2</td>
<td>R21C32[1][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n6826_s22/F</td>
</tr>
<tr>
<td>14.045</td>
<td>0.421</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C31[1][A]</td>
<td>picorv32_core/riscv32_alu_u1/n6826_s17/I0</td>
</tr>
<tr>
<td>14.867</td>
<td>0.822</td>
<td>tINS</td>
<td>RF</td>
<td>2</td>
<td>R21C31[1][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n6826_s17/F</td>
</tr>
<tr>
<td>14.878</td>
<td>0.011</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R21C31[2][B]</td>
<td>picorv32_core/riscv32_alu_u1/n6826_s12/I2</td>
</tr>
<tr>
<td>15.504</td>
<td>0.626</td>
<td>tINS</td>
<td>FF</td>
<td>17</td>
<td>R21C31[2][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n6826_s12/F</td>
</tr>
<tr>
<td>18.272</td>
<td>2.768</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R16C39[3][A]</td>
<td>picorv32_core/riscv32_alu_u1/n6862_s8/I0</td>
</tr>
<tr>
<td>19.304</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R16C39[3][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n6862_s8/F</td>
</tr>
<tr>
<td>20.593</td>
<td>1.289</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R21C39[2][A]</td>
<td>picorv32_core/riscv32_alu_u1/n6862_s7/I0</td>
</tr>
<tr>
<td>21.219</td>
<td>0.626</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R21C39[2][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n6862_s7/F</td>
</tr>
<tr>
<td>21.219</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R21C39[2][A]</td>
<td style=" font-weight:bold;">picorv32_core/riscv32_alu_u1/risc_v_pc_13_s1/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>20.000</td>
<td>20.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>20.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>865</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>21.226</td>
<td>0.244</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C39[2][A]</td>
<td>picorv32_core/riscv32_alu_u1/risc_v_pc_13_s1/CLK</td>
</tr>
<tr>
<td>20.826</td>
<td>-0.400</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R21C39[2][A]</td>
<td>picorv32_core/riscv32_alu_u1/risc_v_pc_13_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>20.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>14</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.982, 80.100%; route: 0.244, 19.900%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 9.884, 49.437%; route: 9.651, 48.271%; tC2Q: 0.458, 2.292%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.982, 80.100%; route: 0.244, 19.900%</td>
</tr>
</table>
<h3>Path5</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-0.380</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>21.205</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>20.826</td>
</tr>
<tr>
<td class="label">From</td>
<td>picorv32_core/riscv32_alu_u1/op1num_5_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>picorv32_core/riscv32_alu_u1/reg_wdata_19_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>865</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.226</td>
<td>0.244</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C38[0][A]</td>
<td>picorv32_core/riscv32_alu_u1/op1num_5_s0/CLK</td>
</tr>
<tr>
<td>1.684</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>11</td>
<td>R20C38[0][A]</td>
<td style=" font-weight:bold;">picorv32_core/riscv32_alu_u1/op1num_5_s0/Q</td>
</tr>
<tr>
<td>5.108</td>
<td>3.424</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R16C23[3][A]</td>
<td>picorv32_core/riscv32_alu_u1/n57_s5/I1</td>
</tr>
<tr>
<td>5.930</td>
<td>0.822</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>R16C23[3][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n57_s5/F</td>
</tr>
<tr>
<td>7.708</td>
<td>1.778</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R16C20[1][A]</td>
<td>picorv32_core/riscv32_alu_u1/n57_s3/I1</td>
</tr>
<tr>
<td>8.334</td>
<td>0.626</td>
<td>tINS</td>
<td>FF</td>
<td>4</td>
<td>R16C20[1][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n57_s3/F</td>
</tr>
<tr>
<td>9.640</td>
<td>1.306</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R13C19[0][B]</td>
<td>picorv32_core/riscv32_alu_u1/n5948_s59/I1</td>
</tr>
<tr>
<td>10.739</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R13C19[0][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n5948_s59/F</td>
</tr>
<tr>
<td>10.744</td>
<td>0.005</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R13C19[3][A]</td>
<td>picorv32_core/riscv32_alu_u1/n5948_s56/I0</td>
</tr>
<tr>
<td>11.843</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R13C19[3][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n5948_s56/F</td>
</tr>
<tr>
<td>15.235</td>
<td>3.392</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R12C23[3][B]</td>
<td>picorv32_core/riscv32_alu_u1/n5948_s47/I3</td>
</tr>
<tr>
<td>15.861</td>
<td>0.626</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R12C23[3][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n5948_s47/F</td>
</tr>
<tr>
<td>17.799</td>
<td>1.938</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R12C36[3][A]</td>
<td>picorv32_core/riscv32_alu_u1/n5948_s38/I2</td>
</tr>
<tr>
<td>18.860</td>
<td>1.061</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R12C36[3][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n5948_s38/F</td>
</tr>
<tr>
<td>19.279</td>
<td>0.419</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R12C37[1][B]</td>
<td>picorv32_core/riscv32_alu_u1/n5948_s34/I2</td>
</tr>
<tr>
<td>20.101</td>
<td>0.822</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R12C37[1][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n5948_s34/F</td>
</tr>
<tr>
<td>20.106</td>
<td>0.005</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R12C37[0][A]</td>
<td>picorv32_core/riscv32_alu_u1/n5948_s33/I1</td>
</tr>
<tr>
<td>21.205</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R12C37[0][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n5948_s33/F</td>
</tr>
<tr>
<td>21.205</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R12C37[0][A]</td>
<td style=" font-weight:bold;">picorv32_core/riscv32_alu_u1/reg_wdata_19_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>20.000</td>
<td>20.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>20.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>865</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>21.226</td>
<td>0.244</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R12C37[0][A]</td>
<td>picorv32_core/riscv32_alu_u1/reg_wdata_19_s0/CLK</td>
</tr>
<tr>
<td>20.826</td>
<td>-0.400</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R12C37[0][A]</td>
<td>picorv32_core/riscv32_alu_u1/reg_wdata_19_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>20.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>9</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.982, 80.100%; route: 0.244, 19.900%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 7.254, 36.307%; route: 12.267, 61.399%; tC2Q: 0.458, 2.294%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.982, 80.100%; route: 0.244, 19.900%</td>
</tr>
</table>
<h3>Path6</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-0.372</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>21.198</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>20.826</td>
</tr>
<tr>
<td class="label">From</td>
<td>picorv32_core/riscv32_alu_u1/op1num_19_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>picorv32_core/riscv32_alu_u1/reg_wdata_21_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>865</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.226</td>
<td>0.244</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C37[0][A]</td>
<td>picorv32_core/riscv32_alu_u1/op1num_19_s0/CLK</td>
</tr>
<tr>
<td>1.684</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>9</td>
<td>R11C37[0][A]</td>
<td style=" font-weight:bold;">picorv32_core/riscv32_alu_u1/op1num_19_s0/Q</td>
</tr>
<tr>
<td>4.941</td>
<td>3.257</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R16C22[2][A]</td>
<td>picorv32_core/riscv32_alu_u1/n43_s4/I1</td>
</tr>
<tr>
<td>6.040</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>R16C22[2][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n43_s4/F</td>
</tr>
<tr>
<td>8.304</td>
<td>2.264</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R17C19[0][B]</td>
<td>picorv32_core/riscv32_alu_u1/n43_s2/I1</td>
</tr>
<tr>
<td>9.403</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>R17C19[0][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n43_s2/F</td>
</tr>
<tr>
<td>9.904</td>
<td>0.501</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R17C21[0][A]</td>
<td>picorv32_core/riscv32_alu_u1/n5944_s56/I0</td>
</tr>
<tr>
<td>11.003</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R17C21[0][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n5944_s56/F</td>
</tr>
<tr>
<td>11.824</td>
<td>0.821</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R17C23[0][B]</td>
<td>picorv32_core/riscv32_alu_u1/n5944_s54/I1</td>
</tr>
<tr>
<td>12.923</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R17C23[0][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n5944_s54/F</td>
</tr>
<tr>
<td>12.928</td>
<td>0.005</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R17C23[1][A]</td>
<td>picorv32_core/riscv32_alu_u1/n5944_s45/I2</td>
</tr>
<tr>
<td>14.027</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>R17C23[1][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n5944_s45/F</td>
</tr>
<tr>
<td>16.939</td>
<td>2.912</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R12C20[1][A]</td>
<td>picorv32_core/riscv32_alu_u1/n5944_s40/I2</td>
</tr>
<tr>
<td>17.565</td>
<td>0.626</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R12C20[1][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n5944_s40/F</td>
</tr>
<tr>
<td>19.339</td>
<td>1.773</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R13C20[3][A]</td>
<td>picorv32_core/riscv32_alu_u1/n5944_s36/I1</td>
</tr>
<tr>
<td>20.371</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R13C20[3][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n5944_s36/F</td>
</tr>
<tr>
<td>20.376</td>
<td>0.005</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R13C20[1][A]</td>
<td>picorv32_core/riscv32_alu_u1/n5944_s33/I3</td>
</tr>
<tr>
<td>21.198</td>
<td>0.822</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R13C20[1][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n5944_s33/F</td>
</tr>
<tr>
<td>21.198</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R13C20[1][A]</td>
<td style=" font-weight:bold;">picorv32_core/riscv32_alu_u1/reg_wdata_21_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>20.000</td>
<td>20.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>20.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>865</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>21.226</td>
<td>0.244</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C20[1][A]</td>
<td>picorv32_core/riscv32_alu_u1/reg_wdata_21_s0/CLK</td>
</tr>
<tr>
<td>20.826</td>
<td>-0.400</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R13C20[1][A]</td>
<td>picorv32_core/riscv32_alu_u1/reg_wdata_21_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>20.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>9</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.982, 80.100%; route: 0.244, 19.900%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 7.975, 39.931%; route: 11.539, 57.775%; tC2Q: 0.458, 2.295%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.982, 80.100%; route: 0.244, 19.900%</td>
</tr>
</table>
<h3>Path7</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-0.323</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>21.149</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>20.826</td>
</tr>
<tr>
<td class="label">From</td>
<td>picorv32_core/riscv32_alu_u1/reg_raddr_3_s3</td>
</tr>
<tr>
<td class="label">To</td>
<td>picorv32_core/riscv32_alu_u1/mem_wdata_11_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>865</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.226</td>
<td>0.244</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C26[1][B]</td>
<td>picorv32_core/riscv32_alu_u1/reg_raddr_3_s3/CLK</td>
</tr>
<tr>
<td>1.684</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>6</td>
<td>R11C26[1][B]</td>
<td style=" font-weight:bold;">picorv32_core/riscv32_alu_u1/reg_raddr_3_s3/Q</td>
</tr>
<tr>
<td>2.834</td>
<td>1.150</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R15C27[3][B]</td>
<td>picorv32_core/riscv32_alu_u1/n68_s7/I2</td>
</tr>
<tr>
<td>3.933</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>15</td>
<td>R15C27[3][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n68_s7/F</td>
</tr>
<tr>
<td>6.053</td>
<td>2.120</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R7C16[0][B]</td>
<td>picorv32_core/riscv32_alu_u1/n51_s10/I0</td>
</tr>
<tr>
<td>7.152</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>25</td>
<td>R7C16[0][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n51_s10/F</td>
</tr>
<tr>
<td>10.951</td>
<td>3.799</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R23C42[0][B]</td>
<td>picorv32_core/riscv32_alu_u1/n79_s4/I2</td>
</tr>
<tr>
<td>12.050</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R23C42[0][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n79_s4/F</td>
</tr>
<tr>
<td>12.055</td>
<td>0.005</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R23C42[0][A]</td>
<td>picorv32_core/riscv32_alu_u1/n79_s5/I1</td>
</tr>
<tr>
<td>13.154</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>11</td>
<td>R23C42[0][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n79_s5/F</td>
</tr>
<tr>
<td>16.418</td>
<td>3.263</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R12C25[2][A]</td>
<td>picorv32_core/riscv32_alu_u1/n2409_s8/I1</td>
</tr>
<tr>
<td>17.240</td>
<td>0.822</td>
<td>tINS</td>
<td>FF</td>
<td>4</td>
<td>R12C25[2][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n2409_s8/F</td>
</tr>
<tr>
<td>20.327</td>
<td>3.087</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R21C38[0][A]</td>
<td>picorv32_core/riscv32_alu_u1/n2438_s6/I3</td>
</tr>
<tr>
<td>21.149</td>
<td>0.822</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R21C38[0][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n2438_s6/F</td>
</tr>
<tr>
<td>21.149</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R21C38[0][A]</td>
<td style=" font-weight:bold;">picorv32_core/riscv32_alu_u1/mem_wdata_11_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>20.000</td>
<td>20.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>20.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>865</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>21.226</td>
<td>0.244</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C38[0][A]</td>
<td>picorv32_core/riscv32_alu_u1/mem_wdata_11_s0/CLK</td>
</tr>
<tr>
<td>20.826</td>
<td>-0.400</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R21C38[0][A]</td>
<td>picorv32_core/riscv32_alu_u1/mem_wdata_11_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>20.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>7</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.982, 80.100%; route: 0.244, 19.900%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 6.040, 30.316%; route: 13.425, 67.383%; tC2Q: 0.458, 2.300%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.982, 80.100%; route: 0.244, 19.900%</td>
</tr>
</table>
<h3>Path8</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-0.323</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>21.149</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>20.826</td>
</tr>
<tr>
<td class="label">From</td>
<td>picorv32_core/riscv32_alu_u1/reg_raddr_3_s3</td>
</tr>
<tr>
<td class="label">To</td>
<td>picorv32_core/riscv32_alu_u1/mem_wdata_19_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>865</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.226</td>
<td>0.244</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C26[1][B]</td>
<td>picorv32_core/riscv32_alu_u1/reg_raddr_3_s3/CLK</td>
</tr>
<tr>
<td>1.684</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>6</td>
<td>R11C26[1][B]</td>
<td style=" font-weight:bold;">picorv32_core/riscv32_alu_u1/reg_raddr_3_s3/Q</td>
</tr>
<tr>
<td>2.834</td>
<td>1.150</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R15C27[3][B]</td>
<td>picorv32_core/riscv32_alu_u1/n68_s7/I2</td>
</tr>
<tr>
<td>3.933</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>15</td>
<td>R15C27[3][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n68_s7/F</td>
</tr>
<tr>
<td>6.053</td>
<td>2.120</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R7C16[0][B]</td>
<td>picorv32_core/riscv32_alu_u1/n51_s10/I0</td>
</tr>
<tr>
<td>7.152</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>25</td>
<td>R7C16[0][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n51_s10/F</td>
</tr>
<tr>
<td>10.951</td>
<td>3.799</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R23C42[0][B]</td>
<td>picorv32_core/riscv32_alu_u1/n79_s4/I2</td>
</tr>
<tr>
<td>12.050</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R23C42[0][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n79_s4/F</td>
</tr>
<tr>
<td>12.055</td>
<td>0.005</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R23C42[0][A]</td>
<td>picorv32_core/riscv32_alu_u1/n79_s5/I1</td>
</tr>
<tr>
<td>13.154</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>11</td>
<td>R23C42[0][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n79_s5/F</td>
</tr>
<tr>
<td>16.418</td>
<td>3.263</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R12C25[2][A]</td>
<td>picorv32_core/riscv32_alu_u1/n2409_s8/I1</td>
</tr>
<tr>
<td>17.240</td>
<td>0.822</td>
<td>tINS</td>
<td>FF</td>
<td>4</td>
<td>R12C25[2][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n2409_s8/F</td>
</tr>
<tr>
<td>20.327</td>
<td>3.087</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R21C38[0][B]</td>
<td>picorv32_core/riscv32_alu_u1/n2422_s6/I0</td>
</tr>
<tr>
<td>21.149</td>
<td>0.822</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R21C38[0][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n2422_s6/F</td>
</tr>
<tr>
<td>21.149</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R21C38[0][B]</td>
<td style=" font-weight:bold;">picorv32_core/riscv32_alu_u1/mem_wdata_19_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>20.000</td>
<td>20.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>20.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>865</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>21.226</td>
<td>0.244</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C38[0][B]</td>
<td>picorv32_core/riscv32_alu_u1/mem_wdata_19_s0/CLK</td>
</tr>
<tr>
<td>20.826</td>
<td>-0.400</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R21C38[0][B]</td>
<td>picorv32_core/riscv32_alu_u1/mem_wdata_19_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>20.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>7</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.982, 80.100%; route: 0.244, 19.900%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 6.040, 30.316%; route: 13.425, 67.383%; tC2Q: 0.458, 2.300%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.982, 80.100%; route: 0.244, 19.900%</td>
</tr>
</table>
<h3>Path9</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-0.279</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>21.104</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>20.826</td>
</tr>
<tr>
<td class="label">From</td>
<td>picorv32_core/riscv32_alu_u1/op1num_2_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>picorv32_core/riscv32_alu_u1/reg_wdata_31_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>865</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.226</td>
<td>0.244</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R23C17[2][A]</td>
<td>picorv32_core/riscv32_alu_u1/op1num_2_s0/CLK</td>
</tr>
<tr>
<td>1.684</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>9</td>
<td>R23C17[2][A]</td>
<td style=" font-weight:bold;">picorv32_core/riscv32_alu_u1/op1num_2_s0/Q</td>
</tr>
<tr>
<td>5.108</td>
<td>3.424</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R16C40[1][A]</td>
<td>picorv32_core/riscv32_alu_u1/op1_add_op2_res_2_s/I0</td>
</tr>
<tr>
<td>6.153</td>
<td>1.045</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R16C40[1][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/op1_add_op2_res_2_s/COUT</td>
</tr>
<tr>
<td>6.153</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R16C40[1][B]</td>
<td>picorv32_core/riscv32_alu_u1/op1_add_op2_res_3_s/CIN</td>
</tr>
<tr>
<td>6.210</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R16C40[1][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/op1_add_op2_res_3_s/COUT</td>
</tr>
<tr>
<td>6.210</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R16C40[2][A]</td>
<td>picorv32_core/riscv32_alu_u1/op1_add_op2_res_4_s/CIN</td>
</tr>
<tr>
<td>6.267</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R16C40[2][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/op1_add_op2_res_4_s/COUT</td>
</tr>
<tr>
<td>6.267</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R16C40[2][B]</td>
<td>picorv32_core/riscv32_alu_u1/op1_add_op2_res_5_s/CIN</td>
</tr>
<tr>
<td>6.324</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R16C40[2][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/op1_add_op2_res_5_s/COUT</td>
</tr>
<tr>
<td>6.324</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R16C41[0][A]</td>
<td>picorv32_core/riscv32_alu_u1/op1_add_op2_res_6_s/CIN</td>
</tr>
<tr>
<td>6.381</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R16C41[0][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/op1_add_op2_res_6_s/COUT</td>
</tr>
<tr>
<td>6.381</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R16C41[0][B]</td>
<td>picorv32_core/riscv32_alu_u1/op1_add_op2_res_7_s/CIN</td>
</tr>
<tr>
<td>6.438</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R16C41[0][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/op1_add_op2_res_7_s/COUT</td>
</tr>
<tr>
<td>6.438</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R16C41[1][A]</td>
<td>picorv32_core/riscv32_alu_u1/op1_add_op2_res_8_s/CIN</td>
</tr>
<tr>
<td>6.495</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R16C41[1][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/op1_add_op2_res_8_s/COUT</td>
</tr>
<tr>
<td>6.495</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R16C41[1][B]</td>
<td>picorv32_core/riscv32_alu_u1/op1_add_op2_res_9_s/CIN</td>
</tr>
<tr>
<td>6.552</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R16C41[1][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/op1_add_op2_res_9_s/COUT</td>
</tr>
<tr>
<td>6.552</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R16C41[2][A]</td>
<td>picorv32_core/riscv32_alu_u1/op1_add_op2_res_10_s/CIN</td>
</tr>
<tr>
<td>6.609</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R16C41[2][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/op1_add_op2_res_10_s/COUT</td>
</tr>
<tr>
<td>6.609</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R16C41[2][B]</td>
<td>picorv32_core/riscv32_alu_u1/op1_add_op2_res_11_s/CIN</td>
</tr>
<tr>
<td>6.666</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R16C41[2][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/op1_add_op2_res_11_s/COUT</td>
</tr>
<tr>
<td>6.666</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R16C42[0][A]</td>
<td>picorv32_core/riscv32_alu_u1/op1_add_op2_res_12_s/CIN</td>
</tr>
<tr>
<td>6.723</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R16C42[0][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/op1_add_op2_res_12_s/COUT</td>
</tr>
<tr>
<td>6.723</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R16C42[0][B]</td>
<td>picorv32_core/riscv32_alu_u1/op1_add_op2_res_13_s/CIN</td>
</tr>
<tr>
<td>6.780</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R16C42[0][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/op1_add_op2_res_13_s/COUT</td>
</tr>
<tr>
<td>6.780</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R16C42[1][A]</td>
<td>picorv32_core/riscv32_alu_u1/op1_add_op2_res_14_s/CIN</td>
</tr>
<tr>
<td>6.837</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R16C42[1][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/op1_add_op2_res_14_s/COUT</td>
</tr>
<tr>
<td>6.837</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R16C42[1][B]</td>
<td>picorv32_core/riscv32_alu_u1/op1_add_op2_res_15_s/CIN</td>
</tr>
<tr>
<td>6.894</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R16C42[1][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/op1_add_op2_res_15_s/COUT</td>
</tr>
<tr>
<td>6.894</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R16C42[2][A]</td>
<td>picorv32_core/riscv32_alu_u1/op1_add_op2_res_16_s/CIN</td>
</tr>
<tr>
<td>6.951</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R16C42[2][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/op1_add_op2_res_16_s/COUT</td>
</tr>
<tr>
<td>6.951</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R16C42[2][B]</td>
<td>picorv32_core/riscv32_alu_u1/op1_add_op2_res_17_s/CIN</td>
</tr>
<tr>
<td>7.008</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R16C42[2][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/op1_add_op2_res_17_s/COUT</td>
</tr>
<tr>
<td>7.008</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R16C43[0][A]</td>
<td>picorv32_core/riscv32_alu_u1/op1_add_op2_res_18_s/CIN</td>
</tr>
<tr>
<td>7.065</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R16C43[0][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/op1_add_op2_res_18_s/COUT</td>
</tr>
<tr>
<td>7.065</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R16C43[0][B]</td>
<td>picorv32_core/riscv32_alu_u1/op1_add_op2_res_19_s/CIN</td>
</tr>
<tr>
<td>7.122</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R16C43[0][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/op1_add_op2_res_19_s/COUT</td>
</tr>
<tr>
<td>7.122</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R16C43[1][A]</td>
<td>picorv32_core/riscv32_alu_u1/op1_add_op2_res_20_s/CIN</td>
</tr>
<tr>
<td>7.179</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R16C43[1][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/op1_add_op2_res_20_s/COUT</td>
</tr>
<tr>
<td>7.179</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R16C43[1][B]</td>
<td>picorv32_core/riscv32_alu_u1/op1_add_op2_res_21_s/CIN</td>
</tr>
<tr>
<td>7.236</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R16C43[1][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/op1_add_op2_res_21_s/COUT</td>
</tr>
<tr>
<td>7.236</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R16C43[2][A]</td>
<td>picorv32_core/riscv32_alu_u1/op1_add_op2_res_22_s/CIN</td>
</tr>
<tr>
<td>7.293</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R16C43[2][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/op1_add_op2_res_22_s/COUT</td>
</tr>
<tr>
<td>7.293</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R16C43[2][B]</td>
<td>picorv32_core/riscv32_alu_u1/op1_add_op2_res_23_s/CIN</td>
</tr>
<tr>
<td>7.350</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R16C43[2][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/op1_add_op2_res_23_s/COUT</td>
</tr>
<tr>
<td>7.350</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R16C44[0][A]</td>
<td>picorv32_core/riscv32_alu_u1/op1_add_op2_res_24_s/CIN</td>
</tr>
<tr>
<td>7.407</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R16C44[0][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/op1_add_op2_res_24_s/COUT</td>
</tr>
<tr>
<td>7.407</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R16C44[0][B]</td>
<td>picorv32_core/riscv32_alu_u1/op1_add_op2_res_25_s/CIN</td>
</tr>
<tr>
<td>7.464</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R16C44[0][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/op1_add_op2_res_25_s/COUT</td>
</tr>
<tr>
<td>7.464</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R16C44[1][A]</td>
<td>picorv32_core/riscv32_alu_u1/op1_add_op2_res_26_s/CIN</td>
</tr>
<tr>
<td>7.521</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R16C44[1][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/op1_add_op2_res_26_s/COUT</td>
</tr>
<tr>
<td>7.521</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R16C44[1][B]</td>
<td>picorv32_core/riscv32_alu_u1/op1_add_op2_res_27_s/CIN</td>
</tr>
<tr>
<td>7.578</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R16C44[1][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/op1_add_op2_res_27_s/COUT</td>
</tr>
<tr>
<td>7.578</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R16C44[2][A]</td>
<td>picorv32_core/riscv32_alu_u1/op1_add_op2_res_28_s/CIN</td>
</tr>
<tr>
<td>7.635</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R16C44[2][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/op1_add_op2_res_28_s/COUT</td>
</tr>
<tr>
<td>7.635</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R16C44[2][B]</td>
<td>picorv32_core/riscv32_alu_u1/op1_add_op2_res_29_s/CIN</td>
</tr>
<tr>
<td>7.692</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R16C44[2][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/op1_add_op2_res_29_s/COUT</td>
</tr>
<tr>
<td>7.692</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R16C45[0][A]</td>
<td>picorv32_core/riscv32_alu_u1/op1_add_op2_res_30_s/CIN</td>
</tr>
<tr>
<td>7.749</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R16C45[0][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/op1_add_op2_res_30_s/COUT</td>
</tr>
<tr>
<td>7.749</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R16C45[0][B]</td>
<td>picorv32_core/riscv32_alu_u1/op1_add_op2_res_31_s/CIN</td>
</tr>
<tr>
<td>8.312</td>
<td>0.563</td>
<td>tINS</td>
<td>FF</td>
<td>4</td>
<td>R16C45[0][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/op1_add_op2_res_31_s/SUM</td>
</tr>
<tr>
<td>12.852</td>
<td>4.540</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R16C16[3][A]</td>
<td>picorv32_core/riscv32_alu_u1/n5924_s75/I1</td>
</tr>
<tr>
<td>13.884</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R16C16[3][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n5924_s75/F</td>
</tr>
<tr>
<td>13.890</td>
<td>0.005</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R16C16[1][A]</td>
<td>picorv32_core/riscv32_alu_u1/n5924_s62/I2</td>
</tr>
<tr>
<td>14.712</td>
<td>0.822</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R16C16[1][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n5924_s62/F</td>
</tr>
<tr>
<td>16.816</td>
<td>2.104</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R15C16[0][B]</td>
<td>picorv32_core/riscv32_alu_u1/n5924_s48/I3</td>
</tr>
<tr>
<td>17.618</td>
<td>0.802</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R15C16[0][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n5924_s48/F</td>
</tr>
<tr>
<td>18.037</td>
<td>0.419</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R15C15[3][A]</td>
<td>picorv32_core/riscv32_alu_u1/n5924_s37/I3</td>
</tr>
<tr>
<td>18.663</td>
<td>0.626</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R15C15[3][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n5924_s37/F</td>
</tr>
<tr>
<td>20.282</td>
<td>1.620</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R16C18[1][B]</td>
<td>picorv32_core/riscv32_alu_u1/n5924_s33/I3</td>
</tr>
<tr>
<td>21.104</td>
<td>0.822</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R16C18[1][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n5924_s33/F</td>
</tr>
<tr>
<td>21.104</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R16C18[1][B]</td>
<td style=" font-weight:bold;">picorv32_core/riscv32_alu_u1/reg_wdata_31_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>20.000</td>
<td>20.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>20.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>865</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>21.226</td>
<td>0.244</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R16C18[1][B]</td>
<td>picorv32_core/riscv32_alu_u1/reg_wdata_31_s0/CLK</td>
</tr>
<tr>
<td>20.826</td>
<td>-0.400</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R16C18[1][B]</td>
<td>picorv32_core/riscv32_alu_u1/reg_wdata_31_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>20.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>11</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.982, 80.100%; route: 0.244, 19.900%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 7.308, 36.763%; route: 12.112, 60.931%; tC2Q: 0.458, 2.306%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.982, 80.100%; route: 0.244, 19.900%</td>
</tr>
</table>
<h3>Path10</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-0.246</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>21.071</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>20.826</td>
</tr>
<tr>
<td class="label">From</td>
<td>picorv32_core/riscv32_alu_u1/instruction_reg_14_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>picorv32_core/riscv32_alu_u1/reg_wdata_23_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>865</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.226</td>
<td>0.244</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C29[1][A]</td>
<td>picorv32_core/riscv32_alu_u1/instruction_reg_14_s0/CLK</td>
</tr>
<tr>
<td>1.684</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>113</td>
<td>R13C29[1][A]</td>
<td style=" font-weight:bold;">picorv32_core/riscv32_alu_u1/instruction_reg_14_s0/Q</td>
</tr>
<tr>
<td>4.562</td>
<td>2.878</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R6C15[0][A]</td>
<td>picorv32_core/riscv32_alu_u1/n2406_s9/I2</td>
</tr>
<tr>
<td>5.594</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>70</td>
<td>R6C15[0][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n2406_s9/F</td>
</tr>
<tr>
<td>9.249</td>
<td>3.655</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R20C29[0][A]</td>
<td>picorv32_core/riscv32_alu_u1/n6958_s23/I1</td>
</tr>
<tr>
<td>10.348</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>6</td>
<td>R20C29[0][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n6958_s23/F</td>
</tr>
<tr>
<td>11.339</td>
<td>0.991</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R13C29[0][B]</td>
<td>picorv32_core/riscv32_alu_u1/n5926_s51/I0</td>
</tr>
<tr>
<td>12.371</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>5</td>
<td>R13C29[0][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n5926_s51/F</td>
</tr>
<tr>
<td>16.931</td>
<td>4.560</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R21C21[0][A]</td>
<td>picorv32_core/riscv32_alu_u1/n5940_s37/I2</td>
</tr>
<tr>
<td>17.963</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R21C21[0][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n5940_s37/F</td>
</tr>
<tr>
<td>19.422</td>
<td>1.459</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R21C20[3][A]</td>
<td>picorv32_core/riscv32_alu_u1/n5940_s36/I0</td>
</tr>
<tr>
<td>20.244</td>
<td>0.822</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R21C20[3][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n5940_s36/F</td>
</tr>
<tr>
<td>20.249</td>
<td>0.005</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R21C20[2][B]</td>
<td>picorv32_core/riscv32_alu_u1/n5940_s33/I3</td>
</tr>
<tr>
<td>21.071</td>
<td>0.822</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R21C20[2][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n5940_s33/F</td>
</tr>
<tr>
<td>21.071</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R21C20[2][B]</td>
<td style=" font-weight:bold;">picorv32_core/riscv32_alu_u1/reg_wdata_23_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>20.000</td>
<td>20.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>20.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>865</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>21.226</td>
<td>0.244</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C20[2][B]</td>
<td>picorv32_core/riscv32_alu_u1/reg_wdata_23_s0/CLK</td>
</tr>
<tr>
<td>20.826</td>
<td>-0.400</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R21C20[2][B]</td>
<td>picorv32_core/riscv32_alu_u1/reg_wdata_23_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>20.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>7</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.982, 80.100%; route: 0.244, 19.900%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 5.839, 29.422%; route: 13.548, 68.268%; tC2Q: 0.458, 2.309%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.982, 80.100%; route: 0.244, 19.900%</td>
</tr>
</table>
<h3>Path11</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-0.238</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>21.064</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>20.826</td>
</tr>
<tr>
<td class="label">From</td>
<td>picorv32_core/riscv32_alu_u1/op1num_1_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>picorv32_core/riscv32_alu_u1/risc_v_pc_9_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>865</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.226</td>
<td>0.244</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R14C15[0][A]</td>
<td>picorv32_core/riscv32_alu_u1/op1num_1_s0/CLK</td>
</tr>
<tr>
<td>1.684</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>12</td>
<td>R14C15[0][A]</td>
<td style=" font-weight:bold;">picorv32_core/riscv32_alu_u1/op1num_1_s0/Q</td>
</tr>
<tr>
<td>4.478</td>
<td>2.793</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C31[1][A]</td>
<td>picorv32_core/riscv32_alu_u1/n246_s64/I0</td>
</tr>
<tr>
<td>5.436</td>
<td>0.958</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C31[1][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n246_s64/COUT</td>
</tr>
<tr>
<td>5.436</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C31[1][B]</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s65/CIN</td>
</tr>
<tr>
<td>5.493</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C31[1][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s65/COUT</td>
</tr>
<tr>
<td>5.493</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C31[2][A]</td>
<td>picorv32_core/riscv32_alu_u1/n246_s65/CIN</td>
</tr>
<tr>
<td>5.550</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C31[2][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n246_s65/COUT</td>
</tr>
<tr>
<td>5.550</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C31[2][B]</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s66/CIN</td>
</tr>
<tr>
<td>5.607</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C31[2][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s66/COUT</td>
</tr>
<tr>
<td>5.607</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C32[0][A]</td>
<td>picorv32_core/riscv32_alu_u1/n246_s66/CIN</td>
</tr>
<tr>
<td>5.664</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C32[0][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n246_s66/COUT</td>
</tr>
<tr>
<td>5.664</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C32[0][B]</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s67/CIN</td>
</tr>
<tr>
<td>5.721</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C32[0][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s67/COUT</td>
</tr>
<tr>
<td>5.721</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C32[1][A]</td>
<td>picorv32_core/riscv32_alu_u1/n246_s67/CIN</td>
</tr>
<tr>
<td>5.778</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C32[1][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n246_s67/COUT</td>
</tr>
<tr>
<td>5.778</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C32[1][B]</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s68/CIN</td>
</tr>
<tr>
<td>5.835</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C32[1][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s68/COUT</td>
</tr>
<tr>
<td>5.835</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C32[2][A]</td>
<td>picorv32_core/riscv32_alu_u1/n246_s68/CIN</td>
</tr>
<tr>
<td>5.892</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C32[2][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n246_s68/COUT</td>
</tr>
<tr>
<td>5.892</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C32[2][B]</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s69/CIN</td>
</tr>
<tr>
<td>5.949</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C32[2][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s69/COUT</td>
</tr>
<tr>
<td>5.949</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C33[0][A]</td>
<td>picorv32_core/riscv32_alu_u1/n246_s69/CIN</td>
</tr>
<tr>
<td>6.006</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C33[0][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n246_s69/COUT</td>
</tr>
<tr>
<td>6.006</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C33[0][B]</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s70/CIN</td>
</tr>
<tr>
<td>6.063</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C33[0][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s70/COUT</td>
</tr>
<tr>
<td>6.063</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C33[1][A]</td>
<td>picorv32_core/riscv32_alu_u1/n246_s70/CIN</td>
</tr>
<tr>
<td>6.120</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C33[1][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n246_s70/COUT</td>
</tr>
<tr>
<td>6.120</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C33[1][B]</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s71/CIN</td>
</tr>
<tr>
<td>6.177</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C33[1][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s71/COUT</td>
</tr>
<tr>
<td>6.177</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C33[2][A]</td>
<td>picorv32_core/riscv32_alu_u1/n246_s71/CIN</td>
</tr>
<tr>
<td>6.234</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C33[2][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n246_s71/COUT</td>
</tr>
<tr>
<td>6.234</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C33[2][B]</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s72/CIN</td>
</tr>
<tr>
<td>6.291</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C33[2][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s72/COUT</td>
</tr>
<tr>
<td>6.291</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C34[0][A]</td>
<td>picorv32_core/riscv32_alu_u1/n246_s72/CIN</td>
</tr>
<tr>
<td>6.348</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C34[0][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n246_s72/COUT</td>
</tr>
<tr>
<td>6.348</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C34[0][B]</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s73/CIN</td>
</tr>
<tr>
<td>6.405</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C34[0][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s73/COUT</td>
</tr>
<tr>
<td>6.405</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C34[1][A]</td>
<td>picorv32_core/riscv32_alu_u1/n246_s73/CIN</td>
</tr>
<tr>
<td>6.462</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C34[1][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n246_s73/COUT</td>
</tr>
<tr>
<td>6.462</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C34[1][B]</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s74/CIN</td>
</tr>
<tr>
<td>6.519</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C34[1][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s74/COUT</td>
</tr>
<tr>
<td>6.519</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C34[2][A]</td>
<td>picorv32_core/riscv32_alu_u1/n246_s74/CIN</td>
</tr>
<tr>
<td>6.576</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C34[2][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n246_s74/COUT</td>
</tr>
<tr>
<td>6.576</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C34[2][B]</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s75/CIN</td>
</tr>
<tr>
<td>6.633</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C34[2][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s75/COUT</td>
</tr>
<tr>
<td>6.633</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C35[0][A]</td>
<td>picorv32_core/riscv32_alu_u1/n246_s75/CIN</td>
</tr>
<tr>
<td>6.690</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C35[0][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n246_s75/COUT</td>
</tr>
<tr>
<td>6.690</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C35[0][B]</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s76/CIN</td>
</tr>
<tr>
<td>6.747</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C35[0][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s76/COUT</td>
</tr>
<tr>
<td>6.747</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C35[1][A]</td>
<td>picorv32_core/riscv32_alu_u1/n246_s76/CIN</td>
</tr>
<tr>
<td>6.804</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C35[1][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n246_s76/COUT</td>
</tr>
<tr>
<td>6.804</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C35[1][B]</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s77/CIN</td>
</tr>
<tr>
<td>6.861</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C35[1][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s77/COUT</td>
</tr>
<tr>
<td>6.861</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C35[2][A]</td>
<td>picorv32_core/riscv32_alu_u1/n246_s77/CIN</td>
</tr>
<tr>
<td>6.918</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C35[2][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n246_s77/COUT</td>
</tr>
<tr>
<td>6.918</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C35[2][B]</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s78/CIN</td>
</tr>
<tr>
<td>6.975</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C35[2][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s78/COUT</td>
</tr>
<tr>
<td>6.975</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C36[0][A]</td>
<td>picorv32_core/riscv32_alu_u1/n246_s78/CIN</td>
</tr>
<tr>
<td>7.032</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C36[0][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n246_s78/COUT</td>
</tr>
<tr>
<td>8.569</td>
<td>1.538</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R22C34[3][B]</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s80/I2</td>
</tr>
<tr>
<td>9.601</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>R22C34[3][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s80/F</td>
</tr>
<tr>
<td>10.416</td>
<td>0.814</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R21C32[3][B]</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_unsigned_s1/I2</td>
</tr>
<tr>
<td>11.515</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>R21C32[3][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/op1_ge_op2_unsigned_s1/F</td>
</tr>
<tr>
<td>11.526</td>
<td>0.011</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R21C32[0][B]</td>
<td>picorv32_core/riscv32_alu_u1/n1673_s10/I3</td>
</tr>
<tr>
<td>12.558</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R21C32[0][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n1673_s10/F</td>
</tr>
<tr>
<td>12.563</td>
<td>0.005</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R21C32[1][B]</td>
<td>picorv32_core/riscv32_alu_u1/n6826_s22/I0</td>
</tr>
<tr>
<td>13.624</td>
<td>1.061</td>
<td>tINS</td>
<td>FR</td>
<td>2</td>
<td>R21C32[1][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n6826_s22/F</td>
</tr>
<tr>
<td>14.045</td>
<td>0.421</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C31[0][B]</td>
<td>picorv32_core/riscv32_alu_u1/n6826_s19/I0</td>
</tr>
<tr>
<td>14.671</td>
<td>0.626</td>
<td>tINS</td>
<td>RF</td>
<td>31</td>
<td>R21C31[0][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n6826_s19/F</td>
</tr>
<tr>
<td>17.332</td>
<td>2.661</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R8C24[0][B]</td>
<td>picorv32_core/riscv32_alu_u1/n6870_s11/I0</td>
</tr>
<tr>
<td>17.958</td>
<td>0.626</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R8C24[0][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n6870_s11/F</td>
</tr>
<tr>
<td>18.762</td>
<td>0.804</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R7C23[1][B]</td>
<td>picorv32_core/riscv32_alu_u1/n6870_s8/I2</td>
</tr>
<tr>
<td>19.823</td>
<td>1.061</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R7C23[1][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n6870_s8/F</td>
</tr>
<tr>
<td>20.242</td>
<td>0.419</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R8C23[1][B]</td>
<td>picorv32_core/riscv32_alu_u1/n6870_s7/I0</td>
</tr>
<tr>
<td>21.064</td>
<td>0.822</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R8C23[1][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n6870_s7/F</td>
</tr>
<tr>
<td>21.064</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R8C23[1][B]</td>
<td style=" font-weight:bold;">picorv32_core/riscv32_alu_u1/risc_v_pc_9_s1/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>20.000</td>
<td>20.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>20.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>865</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>21.226</td>
<td>0.244</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R8C23[1][B]</td>
<td>picorv32_core/riscv32_alu_u1/risc_v_pc_9_s1/CLK</td>
</tr>
<tr>
<td>20.826</td>
<td>-0.400</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R8C23[1][B]</td>
<td>picorv32_core/riscv32_alu_u1/risc_v_pc_9_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>20.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>14</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.982, 80.100%; route: 0.244, 19.900%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 9.913, 49.970%; route: 9.467, 47.720%; tC2Q: 0.458, 2.310%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.982, 80.100%; route: 0.244, 19.900%</td>
</tr>
</table>
<h3>Path12</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-0.218</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>21.044</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>20.826</td>
</tr>
<tr>
<td class="label">From</td>
<td>picorv32_core/riscv32_alu_u1/op1num_1_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>picorv32_core/riscv32_alu_u1/risc_v_pc_14_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>865</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.226</td>
<td>0.244</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R14C15[0][A]</td>
<td>picorv32_core/riscv32_alu_u1/op1num_1_s0/CLK</td>
</tr>
<tr>
<td>1.684</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>12</td>
<td>R14C15[0][A]</td>
<td style=" font-weight:bold;">picorv32_core/riscv32_alu_u1/op1num_1_s0/Q</td>
</tr>
<tr>
<td>4.478</td>
<td>2.793</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C31[1][A]</td>
<td>picorv32_core/riscv32_alu_u1/n246_s64/I0</td>
</tr>
<tr>
<td>5.436</td>
<td>0.958</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C31[1][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n246_s64/COUT</td>
</tr>
<tr>
<td>5.436</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C31[1][B]</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s65/CIN</td>
</tr>
<tr>
<td>5.493</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C31[1][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s65/COUT</td>
</tr>
<tr>
<td>5.493</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C31[2][A]</td>
<td>picorv32_core/riscv32_alu_u1/n246_s65/CIN</td>
</tr>
<tr>
<td>5.550</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C31[2][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n246_s65/COUT</td>
</tr>
<tr>
<td>5.550</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C31[2][B]</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s66/CIN</td>
</tr>
<tr>
<td>5.607</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C31[2][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s66/COUT</td>
</tr>
<tr>
<td>5.607</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C32[0][A]</td>
<td>picorv32_core/riscv32_alu_u1/n246_s66/CIN</td>
</tr>
<tr>
<td>5.664</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C32[0][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n246_s66/COUT</td>
</tr>
<tr>
<td>5.664</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C32[0][B]</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s67/CIN</td>
</tr>
<tr>
<td>5.721</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C32[0][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s67/COUT</td>
</tr>
<tr>
<td>5.721</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C32[1][A]</td>
<td>picorv32_core/riscv32_alu_u1/n246_s67/CIN</td>
</tr>
<tr>
<td>5.778</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C32[1][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n246_s67/COUT</td>
</tr>
<tr>
<td>5.778</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C32[1][B]</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s68/CIN</td>
</tr>
<tr>
<td>5.835</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C32[1][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s68/COUT</td>
</tr>
<tr>
<td>5.835</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C32[2][A]</td>
<td>picorv32_core/riscv32_alu_u1/n246_s68/CIN</td>
</tr>
<tr>
<td>5.892</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C32[2][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n246_s68/COUT</td>
</tr>
<tr>
<td>5.892</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C32[2][B]</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s69/CIN</td>
</tr>
<tr>
<td>5.949</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C32[2][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s69/COUT</td>
</tr>
<tr>
<td>5.949</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C33[0][A]</td>
<td>picorv32_core/riscv32_alu_u1/n246_s69/CIN</td>
</tr>
<tr>
<td>6.006</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C33[0][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n246_s69/COUT</td>
</tr>
<tr>
<td>6.006</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C33[0][B]</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s70/CIN</td>
</tr>
<tr>
<td>6.063</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C33[0][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s70/COUT</td>
</tr>
<tr>
<td>6.063</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C33[1][A]</td>
<td>picorv32_core/riscv32_alu_u1/n246_s70/CIN</td>
</tr>
<tr>
<td>6.120</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C33[1][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n246_s70/COUT</td>
</tr>
<tr>
<td>6.120</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C33[1][B]</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s71/CIN</td>
</tr>
<tr>
<td>6.177</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C33[1][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s71/COUT</td>
</tr>
<tr>
<td>6.177</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C33[2][A]</td>
<td>picorv32_core/riscv32_alu_u1/n246_s71/CIN</td>
</tr>
<tr>
<td>6.234</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C33[2][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n246_s71/COUT</td>
</tr>
<tr>
<td>6.234</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C33[2][B]</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s72/CIN</td>
</tr>
<tr>
<td>6.291</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C33[2][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s72/COUT</td>
</tr>
<tr>
<td>6.291</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C34[0][A]</td>
<td>picorv32_core/riscv32_alu_u1/n246_s72/CIN</td>
</tr>
<tr>
<td>6.348</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C34[0][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n246_s72/COUT</td>
</tr>
<tr>
<td>6.348</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C34[0][B]</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s73/CIN</td>
</tr>
<tr>
<td>6.405</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C34[0][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s73/COUT</td>
</tr>
<tr>
<td>6.405</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C34[1][A]</td>
<td>picorv32_core/riscv32_alu_u1/n246_s73/CIN</td>
</tr>
<tr>
<td>6.462</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C34[1][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n246_s73/COUT</td>
</tr>
<tr>
<td>6.462</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C34[1][B]</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s74/CIN</td>
</tr>
<tr>
<td>6.519</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C34[1][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s74/COUT</td>
</tr>
<tr>
<td>6.519</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C34[2][A]</td>
<td>picorv32_core/riscv32_alu_u1/n246_s74/CIN</td>
</tr>
<tr>
<td>6.576</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C34[2][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n246_s74/COUT</td>
</tr>
<tr>
<td>6.576</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C34[2][B]</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s75/CIN</td>
</tr>
<tr>
<td>6.633</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C34[2][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s75/COUT</td>
</tr>
<tr>
<td>6.633</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C35[0][A]</td>
<td>picorv32_core/riscv32_alu_u1/n246_s75/CIN</td>
</tr>
<tr>
<td>6.690</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C35[0][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n246_s75/COUT</td>
</tr>
<tr>
<td>6.690</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C35[0][B]</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s76/CIN</td>
</tr>
<tr>
<td>6.747</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C35[0][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s76/COUT</td>
</tr>
<tr>
<td>6.747</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C35[1][A]</td>
<td>picorv32_core/riscv32_alu_u1/n246_s76/CIN</td>
</tr>
<tr>
<td>6.804</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C35[1][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n246_s76/COUT</td>
</tr>
<tr>
<td>6.804</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C35[1][B]</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s77/CIN</td>
</tr>
<tr>
<td>6.861</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C35[1][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s77/COUT</td>
</tr>
<tr>
<td>6.861</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C35[2][A]</td>
<td>picorv32_core/riscv32_alu_u1/n246_s77/CIN</td>
</tr>
<tr>
<td>6.918</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C35[2][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n246_s77/COUT</td>
</tr>
<tr>
<td>6.918</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C35[2][B]</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s78/CIN</td>
</tr>
<tr>
<td>6.975</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C35[2][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s78/COUT</td>
</tr>
<tr>
<td>6.975</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C36[0][A]</td>
<td>picorv32_core/riscv32_alu_u1/n246_s78/CIN</td>
</tr>
<tr>
<td>7.032</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C36[0][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n246_s78/COUT</td>
</tr>
<tr>
<td>8.569</td>
<td>1.538</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R22C34[3][B]</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s80/I2</td>
</tr>
<tr>
<td>9.601</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>R22C34[3][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s80/F</td>
</tr>
<tr>
<td>10.416</td>
<td>0.814</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R21C32[3][B]</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_unsigned_s1/I2</td>
</tr>
<tr>
<td>11.515</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>R21C32[3][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/op1_ge_op2_unsigned_s1/F</td>
</tr>
<tr>
<td>11.526</td>
<td>0.011</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R21C32[0][B]</td>
<td>picorv32_core/riscv32_alu_u1/n1673_s10/I3</td>
</tr>
<tr>
<td>12.558</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R21C32[0][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n1673_s10/F</td>
</tr>
<tr>
<td>12.563</td>
<td>0.005</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R21C32[1][B]</td>
<td>picorv32_core/riscv32_alu_u1/n6826_s22/I0</td>
</tr>
<tr>
<td>13.624</td>
<td>1.061</td>
<td>tINS</td>
<td>FR</td>
<td>2</td>
<td>R21C32[1][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n6826_s22/F</td>
</tr>
<tr>
<td>14.045</td>
<td>0.421</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C31[0][B]</td>
<td>picorv32_core/riscv32_alu_u1/n6826_s19/I0</td>
</tr>
<tr>
<td>14.671</td>
<td>0.626</td>
<td>tINS</td>
<td>RF</td>
<td>31</td>
<td>R21C31[0][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n6826_s19/F</td>
</tr>
<tr>
<td>17.023</td>
<td>2.353</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R9C24[0][B]</td>
<td>picorv32_core/riscv32_alu_u1/n6860_s11/I0</td>
</tr>
<tr>
<td>17.649</td>
<td>0.626</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R9C24[0][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n6860_s11/F</td>
</tr>
<tr>
<td>18.938</td>
<td>1.289</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R8C21[0][A]</td>
<td>picorv32_core/riscv32_alu_u1/n6860_s9/I2</td>
</tr>
<tr>
<td>19.999</td>
<td>1.061</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R8C21[0][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n6860_s9/F</td>
</tr>
<tr>
<td>20.418</td>
<td>0.419</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R7C21[1][A]</td>
<td>picorv32_core/riscv32_alu_u1/n6860_s7/I1</td>
</tr>
<tr>
<td>21.044</td>
<td>0.626</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R7C21[1][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n6860_s7/F</td>
</tr>
<tr>
<td>21.044</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R7C21[1][A]</td>
<td style=" font-weight:bold;">picorv32_core/riscv32_alu_u1/risc_v_pc_14_s1/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>20.000</td>
<td>20.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>20.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>865</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>21.226</td>
<td>0.244</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R7C21[1][A]</td>
<td>picorv32_core/riscv32_alu_u1/risc_v_pc_14_s1/CLK</td>
</tr>
<tr>
<td>20.826</td>
<td>-0.400</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R7C21[1][A]</td>
<td>picorv32_core/riscv32_alu_u1/risc_v_pc_14_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>20.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>14</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.982, 80.100%; route: 0.244, 19.900%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 9.717, 49.030%; route: 9.643, 48.657%; tC2Q: 0.458, 2.313%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.982, 80.100%; route: 0.244, 19.900%</td>
</tr>
</table>
<h3>Path13</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-0.190</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>21.015</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>20.826</td>
</tr>
<tr>
<td class="label">From</td>
<td>picorv32_core/riscv32_alu_u1/op1num_0_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>picorv32_core/riscv32_alu_u1/reg_wdata_11_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>865</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.226</td>
<td>0.244</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R25C17[1][B]</td>
<td>picorv32_core/riscv32_alu_u1/op1num_0_s0/CLK</td>
</tr>
<tr>
<td>1.684</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>11</td>
<td>R25C17[1][B]</td>
<td style=" font-weight:bold;">picorv32_core/riscv32_alu_u1/op1num_0_s0/Q</td>
</tr>
<tr>
<td>4.942</td>
<td>3.258</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R16C40[0][A]</td>
<td>picorv32_core/riscv32_alu_u1/op1_add_op2_res_0_s/I0</td>
</tr>
<tr>
<td>5.645</td>
<td>0.703</td>
<td>tINS</td>
<td>FF</td>
<td>22</td>
<td>R16C40[0][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/op1_add_op2_res_0_s/SUM</td>
</tr>
<tr>
<td>9.413</td>
<td>3.768</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R17C14[1][A]</td>
<td>picorv32_core/riscv32_alu_u1/n5982_s38/I1</td>
</tr>
<tr>
<td>10.445</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>10</td>
<td>R17C14[1][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n5982_s38/F</td>
</tr>
<tr>
<td>11.277</td>
<td>0.832</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C12[3][A]</td>
<td>picorv32_core/riscv32_alu_u1/n5924_s50/I3</td>
</tr>
<tr>
<td>11.903</td>
<td>0.626</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>R18C12[3][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n5924_s50/F</td>
</tr>
<tr>
<td>13.366</td>
<td>1.464</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C17[2][B]</td>
<td>picorv32_core/riscv32_alu_u1/n5924_s81/I3</td>
</tr>
<tr>
<td>14.398</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>R18C17[2][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n5924_s81/F</td>
</tr>
<tr>
<td>16.028</td>
<td>1.629</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C29[3][A]</td>
<td>picorv32_core/riscv32_alu_u1/n5956_s47/I2</td>
</tr>
<tr>
<td>16.850</td>
<td>0.822</td>
<td>tINS</td>
<td>FF</td>
<td>8</td>
<td>R18C29[3][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n5956_s47/F</td>
</tr>
<tr>
<td>18.671</td>
<td>1.822</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R14C23[2][B]</td>
<td>picorv32_core/riscv32_alu_u1/n5964_s35/I0</td>
</tr>
<tr>
<td>19.493</td>
<td>0.822</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R14C23[2][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n5964_s35/F</td>
</tr>
<tr>
<td>19.983</td>
<td>0.490</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R14C24[0][B]</td>
<td>picorv32_core/riscv32_alu_u1/n5964_s33/I1</td>
</tr>
<tr>
<td>21.015</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R14C24[0][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n5964_s33/F</td>
</tr>
<tr>
<td>21.015</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R14C24[0][B]</td>
<td style=" font-weight:bold;">picorv32_core/riscv32_alu_u1/reg_wdata_11_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>20.000</td>
<td>20.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>20.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>865</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>21.226</td>
<td>0.244</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R14C24[0][B]</td>
<td>picorv32_core/riscv32_alu_u1/reg_wdata_11_s0/CLK</td>
</tr>
<tr>
<td>20.826</td>
<td>-0.400</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R14C24[0][B]</td>
<td>picorv32_core/riscv32_alu_u1/reg_wdata_11_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>20.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>8</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.982, 80.100%; route: 0.244, 19.900%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 6.069, 30.668%; route: 13.262, 67.016%; tC2Q: 0.458, 2.316%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.982, 80.100%; route: 0.244, 19.900%</td>
</tr>
</table>
<h3>Path14</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-0.143</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>20.969</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>20.826</td>
</tr>
<tr>
<td class="label">From</td>
<td>picorv32_core/riscv32_alu_u1/op1num_0_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>picorv32_core/riscv32_alu_u1/reg_wdata_15_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>865</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.226</td>
<td>0.244</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R25C17[1][B]</td>
<td>picorv32_core/riscv32_alu_u1/op1num_0_s0/CLK</td>
</tr>
<tr>
<td>1.684</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>11</td>
<td>R25C17[1][B]</td>
<td style=" font-weight:bold;">picorv32_core/riscv32_alu_u1/op1num_0_s0/Q</td>
</tr>
<tr>
<td>4.942</td>
<td>3.258</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R16C40[0][A]</td>
<td>picorv32_core/riscv32_alu_u1/op1_add_op2_res_0_s/I0</td>
</tr>
<tr>
<td>5.645</td>
<td>0.703</td>
<td>tINS</td>
<td>FF</td>
<td>22</td>
<td>R16C40[0][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/op1_add_op2_res_0_s/SUM</td>
</tr>
<tr>
<td>9.413</td>
<td>3.768</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R17C14[1][A]</td>
<td>picorv32_core/riscv32_alu_u1/n5982_s38/I1</td>
</tr>
<tr>
<td>10.445</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>10</td>
<td>R17C14[1][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n5982_s38/F</td>
</tr>
<tr>
<td>11.277</td>
<td>0.832</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C12[3][A]</td>
<td>picorv32_core/riscv32_alu_u1/n5924_s50/I3</td>
</tr>
<tr>
<td>11.903</td>
<td>0.626</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>R18C12[3][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n5924_s50/F</td>
</tr>
<tr>
<td>13.366</td>
<td>1.464</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C17[2][B]</td>
<td>picorv32_core/riscv32_alu_u1/n5924_s81/I3</td>
</tr>
<tr>
<td>14.398</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>R18C17[2][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n5924_s81/F</td>
</tr>
<tr>
<td>16.028</td>
<td>1.629</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C29[3][A]</td>
<td>picorv32_core/riscv32_alu_u1/n5956_s47/I2</td>
</tr>
<tr>
<td>16.850</td>
<td>0.822</td>
<td>tINS</td>
<td>FF</td>
<td>8</td>
<td>R18C29[3][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n5956_s47/F</td>
</tr>
<tr>
<td>18.507</td>
<td>1.657</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R8C31[3][A]</td>
<td>picorv32_core/riscv32_alu_u1/n5956_s37/I0</td>
</tr>
<tr>
<td>19.539</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R8C31[3][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n5956_s37/F</td>
</tr>
<tr>
<td>20.343</td>
<td>0.804</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R7C32[1][A]</td>
<td>picorv32_core/riscv32_alu_u1/n5956_s33/I3</td>
</tr>
<tr>
<td>20.969</td>
<td>0.626</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R7C32[1][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n5956_s33/F</td>
</tr>
<tr>
<td>20.969</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R7C32[1][A]</td>
<td style=" font-weight:bold;">picorv32_core/riscv32_alu_u1/reg_wdata_15_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>20.000</td>
<td>20.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>20.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>865</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>21.226</td>
<td>0.244</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R7C32[1][A]</td>
<td>picorv32_core/riscv32_alu_u1/reg_wdata_15_s0/CLK</td>
</tr>
<tr>
<td>20.826</td>
<td>-0.400</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R7C32[1][A]</td>
<td>picorv32_core/riscv32_alu_u1/reg_wdata_15_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>20.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>8</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.982, 80.100%; route: 0.244, 19.900%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 5.873, 29.747%; route: 13.412, 67.932%; tC2Q: 0.458, 2.321%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.982, 80.100%; route: 0.244, 19.900%</td>
</tr>
</table>
<h3>Path15</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-0.138</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>20.964</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>20.826</td>
</tr>
<tr>
<td class="label">From</td>
<td>picorv32_core/riscv32_alu_u1/op1num_1_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>picorv32_core/riscv32_alu_u1/risc_v_pc_26_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>865</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.226</td>
<td>0.244</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R14C15[0][A]</td>
<td>picorv32_core/riscv32_alu_u1/op1num_1_s0/CLK</td>
</tr>
<tr>
<td>1.684</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>12</td>
<td>R14C15[0][A]</td>
<td style=" font-weight:bold;">picorv32_core/riscv32_alu_u1/op1num_1_s0/Q</td>
</tr>
<tr>
<td>4.478</td>
<td>2.793</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C31[1][A]</td>
<td>picorv32_core/riscv32_alu_u1/n246_s64/I0</td>
</tr>
<tr>
<td>5.436</td>
<td>0.958</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C31[1][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n246_s64/COUT</td>
</tr>
<tr>
<td>5.436</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C31[1][B]</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s65/CIN</td>
</tr>
<tr>
<td>5.493</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C31[1][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s65/COUT</td>
</tr>
<tr>
<td>5.493</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C31[2][A]</td>
<td>picorv32_core/riscv32_alu_u1/n246_s65/CIN</td>
</tr>
<tr>
<td>5.550</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C31[2][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n246_s65/COUT</td>
</tr>
<tr>
<td>5.550</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C31[2][B]</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s66/CIN</td>
</tr>
<tr>
<td>5.607</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C31[2][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s66/COUT</td>
</tr>
<tr>
<td>5.607</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C32[0][A]</td>
<td>picorv32_core/riscv32_alu_u1/n246_s66/CIN</td>
</tr>
<tr>
<td>5.664</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C32[0][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n246_s66/COUT</td>
</tr>
<tr>
<td>5.664</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C32[0][B]</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s67/CIN</td>
</tr>
<tr>
<td>5.721</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C32[0][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s67/COUT</td>
</tr>
<tr>
<td>5.721</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C32[1][A]</td>
<td>picorv32_core/riscv32_alu_u1/n246_s67/CIN</td>
</tr>
<tr>
<td>5.778</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C32[1][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n246_s67/COUT</td>
</tr>
<tr>
<td>5.778</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C32[1][B]</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s68/CIN</td>
</tr>
<tr>
<td>5.835</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C32[1][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s68/COUT</td>
</tr>
<tr>
<td>5.835</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C32[2][A]</td>
<td>picorv32_core/riscv32_alu_u1/n246_s68/CIN</td>
</tr>
<tr>
<td>5.892</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C32[2][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n246_s68/COUT</td>
</tr>
<tr>
<td>5.892</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C32[2][B]</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s69/CIN</td>
</tr>
<tr>
<td>5.949</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C32[2][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s69/COUT</td>
</tr>
<tr>
<td>5.949</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C33[0][A]</td>
<td>picorv32_core/riscv32_alu_u1/n246_s69/CIN</td>
</tr>
<tr>
<td>6.006</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C33[0][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n246_s69/COUT</td>
</tr>
<tr>
<td>6.006</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C33[0][B]</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s70/CIN</td>
</tr>
<tr>
<td>6.063</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C33[0][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s70/COUT</td>
</tr>
<tr>
<td>6.063</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C33[1][A]</td>
<td>picorv32_core/riscv32_alu_u1/n246_s70/CIN</td>
</tr>
<tr>
<td>6.120</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C33[1][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n246_s70/COUT</td>
</tr>
<tr>
<td>6.120</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C33[1][B]</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s71/CIN</td>
</tr>
<tr>
<td>6.177</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C33[1][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s71/COUT</td>
</tr>
<tr>
<td>6.177</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C33[2][A]</td>
<td>picorv32_core/riscv32_alu_u1/n246_s71/CIN</td>
</tr>
<tr>
<td>6.234</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C33[2][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n246_s71/COUT</td>
</tr>
<tr>
<td>6.234</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C33[2][B]</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s72/CIN</td>
</tr>
<tr>
<td>6.291</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C33[2][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s72/COUT</td>
</tr>
<tr>
<td>6.291</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C34[0][A]</td>
<td>picorv32_core/riscv32_alu_u1/n246_s72/CIN</td>
</tr>
<tr>
<td>6.348</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C34[0][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n246_s72/COUT</td>
</tr>
<tr>
<td>6.348</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C34[0][B]</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s73/CIN</td>
</tr>
<tr>
<td>6.405</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C34[0][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s73/COUT</td>
</tr>
<tr>
<td>6.405</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C34[1][A]</td>
<td>picorv32_core/riscv32_alu_u1/n246_s73/CIN</td>
</tr>
<tr>
<td>6.462</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C34[1][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n246_s73/COUT</td>
</tr>
<tr>
<td>6.462</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C34[1][B]</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s74/CIN</td>
</tr>
<tr>
<td>6.519</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C34[1][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s74/COUT</td>
</tr>
<tr>
<td>6.519</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C34[2][A]</td>
<td>picorv32_core/riscv32_alu_u1/n246_s74/CIN</td>
</tr>
<tr>
<td>6.576</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C34[2][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n246_s74/COUT</td>
</tr>
<tr>
<td>6.576</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C34[2][B]</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s75/CIN</td>
</tr>
<tr>
<td>6.633</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C34[2][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s75/COUT</td>
</tr>
<tr>
<td>6.633</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C35[0][A]</td>
<td>picorv32_core/riscv32_alu_u1/n246_s75/CIN</td>
</tr>
<tr>
<td>6.690</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C35[0][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n246_s75/COUT</td>
</tr>
<tr>
<td>6.690</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C35[0][B]</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s76/CIN</td>
</tr>
<tr>
<td>6.747</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C35[0][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s76/COUT</td>
</tr>
<tr>
<td>6.747</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C35[1][A]</td>
<td>picorv32_core/riscv32_alu_u1/n246_s76/CIN</td>
</tr>
<tr>
<td>6.804</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C35[1][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n246_s76/COUT</td>
</tr>
<tr>
<td>6.804</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C35[1][B]</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s77/CIN</td>
</tr>
<tr>
<td>6.861</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C35[1][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s77/COUT</td>
</tr>
<tr>
<td>6.861</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C35[2][A]</td>
<td>picorv32_core/riscv32_alu_u1/n246_s77/CIN</td>
</tr>
<tr>
<td>6.918</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C35[2][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n246_s77/COUT</td>
</tr>
<tr>
<td>6.918</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C35[2][B]</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s78/CIN</td>
</tr>
<tr>
<td>6.975</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C35[2][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s78/COUT</td>
</tr>
<tr>
<td>6.975</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C36[0][A]</td>
<td>picorv32_core/riscv32_alu_u1/n246_s78/CIN</td>
</tr>
<tr>
<td>7.032</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C36[0][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n246_s78/COUT</td>
</tr>
<tr>
<td>8.569</td>
<td>1.538</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R22C34[3][B]</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s80/I2</td>
</tr>
<tr>
<td>9.601</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>R22C34[3][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s80/F</td>
</tr>
<tr>
<td>10.416</td>
<td>0.814</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R21C32[3][B]</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_unsigned_s1/I2</td>
</tr>
<tr>
<td>11.515</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>R21C32[3][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/op1_ge_op2_unsigned_s1/F</td>
</tr>
<tr>
<td>11.526</td>
<td>0.011</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R21C32[0][B]</td>
<td>picorv32_core/riscv32_alu_u1/n1673_s10/I3</td>
</tr>
<tr>
<td>12.558</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R21C32[0][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n1673_s10/F</td>
</tr>
<tr>
<td>12.563</td>
<td>0.005</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R21C32[1][B]</td>
<td>picorv32_core/riscv32_alu_u1/n6826_s22/I0</td>
</tr>
<tr>
<td>13.624</td>
<td>1.061</td>
<td>tINS</td>
<td>FR</td>
<td>2</td>
<td>R21C32[1][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n6826_s22/F</td>
</tr>
<tr>
<td>14.045</td>
<td>0.421</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C31[0][B]</td>
<td>picorv32_core/riscv32_alu_u1/n6826_s19/I0</td>
</tr>
<tr>
<td>14.671</td>
<td>0.626</td>
<td>tINS</td>
<td>RF</td>
<td>31</td>
<td>R21C31[0][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n6826_s19/F</td>
</tr>
<tr>
<td>17.318</td>
<td>2.648</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R8C38[2][A]</td>
<td>picorv32_core/riscv32_alu_u1/n6836_s13/I0</td>
</tr>
<tr>
<td>17.944</td>
<td>0.626</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R8C38[2][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n6836_s13/F</td>
</tr>
<tr>
<td>19.233</td>
<td>1.289</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R11C39[0][B]</td>
<td>picorv32_core/riscv32_alu_u1/n6836_s10/I2</td>
</tr>
<tr>
<td>19.859</td>
<td>0.626</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R11C39[0][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n6836_s10/F</td>
</tr>
<tr>
<td>19.865</td>
<td>0.005</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R11C39[2][A]</td>
<td>picorv32_core/riscv32_alu_u1/n6836_s7/I3</td>
</tr>
<tr>
<td>20.964</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R11C39[2][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n6836_s7/F</td>
</tr>
<tr>
<td>20.964</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R11C39[2][A]</td>
<td style=" font-weight:bold;">picorv32_core/riscv32_alu_u1/risc_v_pc_26_s1/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>20.000</td>
<td>20.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>20.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>865</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>21.226</td>
<td>0.244</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C39[2][A]</td>
<td>picorv32_core/riscv32_alu_u1/risc_v_pc_26_s1/CLK</td>
</tr>
<tr>
<td>20.826</td>
<td>-0.400</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R11C39[2][A]</td>
<td>picorv32_core/riscv32_alu_u1/risc_v_pc_26_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>20.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>14</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.982, 80.100%; route: 0.244, 19.900%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 9.755, 49.422%; route: 9.525, 48.255%; tC2Q: 0.458, 2.322%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.982, 80.100%; route: 0.244, 19.900%</td>
</tr>
</table>
<h3>Path16</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-0.126</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>20.952</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>20.826</td>
</tr>
<tr>
<td class="label">From</td>
<td>picorv32_core/riscv32_alu_u1/instruction_reg_14_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>picorv32_core/riscv32_alu_u1/reg_wdata_0_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>865</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.226</td>
<td>0.244</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C29[1][A]</td>
<td>picorv32_core/riscv32_alu_u1/instruction_reg_14_s0/CLK</td>
</tr>
<tr>
<td>1.684</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>113</td>
<td>R13C29[1][A]</td>
<td style=" font-weight:bold;">picorv32_core/riscv32_alu_u1/instruction_reg_14_s0/Q</td>
</tr>
<tr>
<td>4.562</td>
<td>2.878</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R6C15[0][A]</td>
<td>picorv32_core/riscv32_alu_u1/n2406_s9/I2</td>
</tr>
<tr>
<td>5.594</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>70</td>
<td>R6C15[0][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n2406_s9/F</td>
</tr>
<tr>
<td>9.249</td>
<td>3.655</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R20C29[0][A]</td>
<td>picorv32_core/riscv32_alu_u1/n6958_s23/I1</td>
</tr>
<tr>
<td>10.348</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>6</td>
<td>R20C29[0][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n6958_s23/F</td>
</tr>
<tr>
<td>11.339</td>
<td>0.991</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R13C29[0][B]</td>
<td>picorv32_core/riscv32_alu_u1/n5926_s51/I0</td>
</tr>
<tr>
<td>12.371</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>5</td>
<td>R13C29[0][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n5926_s51/F</td>
</tr>
<tr>
<td>15.945</td>
<td>3.574</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R21C28[0][A]</td>
<td>picorv32_core/riscv32_alu_u1/n5980_s38/I0</td>
</tr>
<tr>
<td>16.571</td>
<td>0.626</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>R21C28[0][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n5980_s38/F</td>
</tr>
<tr>
<td>19.014</td>
<td>2.443</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R21C18[3][A]</td>
<td>picorv32_core/riscv32_alu_u1/n5986_s36/I2</td>
</tr>
<tr>
<td>19.640</td>
<td>0.626</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R21C18[3][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n5986_s36/F</td>
</tr>
<tr>
<td>20.130</td>
<td>0.490</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R21C16[1][B]</td>
<td>picorv32_core/riscv32_alu_u1/n5986_s33/I2</td>
</tr>
<tr>
<td>20.952</td>
<td>0.822</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R21C16[1][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n5986_s33/F</td>
</tr>
<tr>
<td>20.952</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R21C16[1][B]</td>
<td style=" font-weight:bold;">picorv32_core/riscv32_alu_u1/reg_wdata_0_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>20.000</td>
<td>20.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>20.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>865</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>21.226</td>
<td>0.244</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C16[1][B]</td>
<td>picorv32_core/riscv32_alu_u1/reg_wdata_0_s0/CLK</td>
</tr>
<tr>
<td>20.826</td>
<td>-0.400</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R21C16[1][B]</td>
<td>picorv32_core/riscv32_alu_u1/reg_wdata_0_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>20.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>7</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.982, 80.100%; route: 0.244, 19.900%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 5.237, 26.549%; route: 14.031, 71.128%; tC2Q: 0.458, 2.324%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.982, 80.100%; route: 0.244, 19.900%</td>
</tr>
</table>
<h3>Path17</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-0.121</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>20.947</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>20.826</td>
</tr>
<tr>
<td class="label">From</td>
<td>picorv32_core/riscv32_alu_u1/op1num_1_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>picorv32_core/riscv32_alu_u1/risc_v_pc_22_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>865</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.226</td>
<td>0.244</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R14C15[0][A]</td>
<td>picorv32_core/riscv32_alu_u1/op1num_1_s0/CLK</td>
</tr>
<tr>
<td>1.684</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>12</td>
<td>R14C15[0][A]</td>
<td style=" font-weight:bold;">picorv32_core/riscv32_alu_u1/op1num_1_s0/Q</td>
</tr>
<tr>
<td>4.478</td>
<td>2.793</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C31[1][A]</td>
<td>picorv32_core/riscv32_alu_u1/n246_s64/I0</td>
</tr>
<tr>
<td>5.436</td>
<td>0.958</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C31[1][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n246_s64/COUT</td>
</tr>
<tr>
<td>5.436</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C31[1][B]</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s65/CIN</td>
</tr>
<tr>
<td>5.493</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C31[1][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s65/COUT</td>
</tr>
<tr>
<td>5.493</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C31[2][A]</td>
<td>picorv32_core/riscv32_alu_u1/n246_s65/CIN</td>
</tr>
<tr>
<td>5.550</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C31[2][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n246_s65/COUT</td>
</tr>
<tr>
<td>5.550</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C31[2][B]</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s66/CIN</td>
</tr>
<tr>
<td>5.607</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C31[2][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s66/COUT</td>
</tr>
<tr>
<td>5.607</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C32[0][A]</td>
<td>picorv32_core/riscv32_alu_u1/n246_s66/CIN</td>
</tr>
<tr>
<td>5.664</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C32[0][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n246_s66/COUT</td>
</tr>
<tr>
<td>5.664</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C32[0][B]</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s67/CIN</td>
</tr>
<tr>
<td>5.721</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C32[0][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s67/COUT</td>
</tr>
<tr>
<td>5.721</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C32[1][A]</td>
<td>picorv32_core/riscv32_alu_u1/n246_s67/CIN</td>
</tr>
<tr>
<td>5.778</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C32[1][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n246_s67/COUT</td>
</tr>
<tr>
<td>5.778</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C32[1][B]</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s68/CIN</td>
</tr>
<tr>
<td>5.835</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C32[1][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s68/COUT</td>
</tr>
<tr>
<td>5.835</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C32[2][A]</td>
<td>picorv32_core/riscv32_alu_u1/n246_s68/CIN</td>
</tr>
<tr>
<td>5.892</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C32[2][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n246_s68/COUT</td>
</tr>
<tr>
<td>5.892</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C32[2][B]</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s69/CIN</td>
</tr>
<tr>
<td>5.949</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C32[2][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s69/COUT</td>
</tr>
<tr>
<td>5.949</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C33[0][A]</td>
<td>picorv32_core/riscv32_alu_u1/n246_s69/CIN</td>
</tr>
<tr>
<td>6.006</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C33[0][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n246_s69/COUT</td>
</tr>
<tr>
<td>6.006</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C33[0][B]</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s70/CIN</td>
</tr>
<tr>
<td>6.063</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C33[0][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s70/COUT</td>
</tr>
<tr>
<td>6.063</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C33[1][A]</td>
<td>picorv32_core/riscv32_alu_u1/n246_s70/CIN</td>
</tr>
<tr>
<td>6.120</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C33[1][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n246_s70/COUT</td>
</tr>
<tr>
<td>6.120</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C33[1][B]</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s71/CIN</td>
</tr>
<tr>
<td>6.177</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C33[1][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s71/COUT</td>
</tr>
<tr>
<td>6.177</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C33[2][A]</td>
<td>picorv32_core/riscv32_alu_u1/n246_s71/CIN</td>
</tr>
<tr>
<td>6.234</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C33[2][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n246_s71/COUT</td>
</tr>
<tr>
<td>6.234</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C33[2][B]</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s72/CIN</td>
</tr>
<tr>
<td>6.291</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C33[2][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s72/COUT</td>
</tr>
<tr>
<td>6.291</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C34[0][A]</td>
<td>picorv32_core/riscv32_alu_u1/n246_s72/CIN</td>
</tr>
<tr>
<td>6.348</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C34[0][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n246_s72/COUT</td>
</tr>
<tr>
<td>6.348</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C34[0][B]</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s73/CIN</td>
</tr>
<tr>
<td>6.405</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C34[0][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s73/COUT</td>
</tr>
<tr>
<td>6.405</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C34[1][A]</td>
<td>picorv32_core/riscv32_alu_u1/n246_s73/CIN</td>
</tr>
<tr>
<td>6.462</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C34[1][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n246_s73/COUT</td>
</tr>
<tr>
<td>6.462</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C34[1][B]</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s74/CIN</td>
</tr>
<tr>
<td>6.519</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C34[1][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s74/COUT</td>
</tr>
<tr>
<td>6.519</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C34[2][A]</td>
<td>picorv32_core/riscv32_alu_u1/n246_s74/CIN</td>
</tr>
<tr>
<td>6.576</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C34[2][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n246_s74/COUT</td>
</tr>
<tr>
<td>6.576</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C34[2][B]</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s75/CIN</td>
</tr>
<tr>
<td>6.633</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C34[2][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s75/COUT</td>
</tr>
<tr>
<td>6.633</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C35[0][A]</td>
<td>picorv32_core/riscv32_alu_u1/n246_s75/CIN</td>
</tr>
<tr>
<td>6.690</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C35[0][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n246_s75/COUT</td>
</tr>
<tr>
<td>6.690</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C35[0][B]</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s76/CIN</td>
</tr>
<tr>
<td>6.747</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C35[0][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s76/COUT</td>
</tr>
<tr>
<td>6.747</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C35[1][A]</td>
<td>picorv32_core/riscv32_alu_u1/n246_s76/CIN</td>
</tr>
<tr>
<td>6.804</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C35[1][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n246_s76/COUT</td>
</tr>
<tr>
<td>6.804</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C35[1][B]</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s77/CIN</td>
</tr>
<tr>
<td>6.861</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C35[1][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s77/COUT</td>
</tr>
<tr>
<td>6.861</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C35[2][A]</td>
<td>picorv32_core/riscv32_alu_u1/n246_s77/CIN</td>
</tr>
<tr>
<td>6.918</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C35[2][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n246_s77/COUT</td>
</tr>
<tr>
<td>6.918</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C35[2][B]</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s78/CIN</td>
</tr>
<tr>
<td>6.975</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C35[2][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s78/COUT</td>
</tr>
<tr>
<td>6.975</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C36[0][A]</td>
<td>picorv32_core/riscv32_alu_u1/n246_s78/CIN</td>
</tr>
<tr>
<td>7.032</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C36[0][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n246_s78/COUT</td>
</tr>
<tr>
<td>8.569</td>
<td>1.538</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R22C34[3][B]</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s80/I2</td>
</tr>
<tr>
<td>9.601</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>R22C34[3][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s80/F</td>
</tr>
<tr>
<td>10.416</td>
<td>0.814</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R21C32[3][B]</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_unsigned_s1/I2</td>
</tr>
<tr>
<td>11.515</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>R21C32[3][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/op1_ge_op2_unsigned_s1/F</td>
</tr>
<tr>
<td>11.526</td>
<td>0.011</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R21C32[0][B]</td>
<td>picorv32_core/riscv32_alu_u1/n1673_s10/I3</td>
</tr>
<tr>
<td>12.558</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R21C32[0][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n1673_s10/F</td>
</tr>
<tr>
<td>12.563</td>
<td>0.005</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R21C32[1][B]</td>
<td>picorv32_core/riscv32_alu_u1/n6826_s22/I0</td>
</tr>
<tr>
<td>13.624</td>
<td>1.061</td>
<td>tINS</td>
<td>FR</td>
<td>2</td>
<td>R21C32[1][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n6826_s22/F</td>
</tr>
<tr>
<td>14.045</td>
<td>0.421</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C31[0][B]</td>
<td>picorv32_core/riscv32_alu_u1/n6826_s19/I0</td>
</tr>
<tr>
<td>14.671</td>
<td>0.626</td>
<td>tINS</td>
<td>RF</td>
<td>31</td>
<td>R21C31[0][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n6826_s19/F</td>
</tr>
<tr>
<td>16.658</td>
<td>1.987</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R16C40[3][B]</td>
<td>picorv32_core/riscv32_alu_u1/n6844_s14/I0</td>
</tr>
<tr>
<td>17.757</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R16C40[3][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n6844_s14/F</td>
</tr>
<tr>
<td>19.216</td>
<td>1.459</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R21C40[0][B]</td>
<td>picorv32_core/riscv32_alu_u1/n6844_s11/I2</td>
</tr>
<tr>
<td>19.842</td>
<td>0.626</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R21C40[0][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n6844_s11/F</td>
</tr>
<tr>
<td>19.848</td>
<td>0.005</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R21C40[2][B]</td>
<td>picorv32_core/riscv32_alu_u1/n6844_s7/I3</td>
</tr>
<tr>
<td>20.947</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R21C40[2][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n6844_s7/F</td>
</tr>
<tr>
<td>20.947</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R21C40[2][B]</td>
<td style=" font-weight:bold;">picorv32_core/riscv32_alu_u1/risc_v_pc_22_s1/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>20.000</td>
<td>20.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>20.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>865</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>21.226</td>
<td>0.244</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C40[2][B]</td>
<td>picorv32_core/riscv32_alu_u1/risc_v_pc_22_s1/CLK</td>
</tr>
<tr>
<td>20.826</td>
<td>-0.400</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R21C40[2][B]</td>
<td>picorv32_core/riscv32_alu_u1/risc_v_pc_22_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>20.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>14</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.982, 80.100%; route: 0.244, 19.900%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 10.228, 51.864%; route: 9.034, 45.812%; tC2Q: 0.458, 2.324%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.982, 80.100%; route: 0.244, 19.900%</td>
</tr>
</table>
<h3>Path18</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-0.112</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>20.938</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>20.826</td>
</tr>
<tr>
<td class="label">From</td>
<td>picorv32_core/riscv32_alu_u1/op1num_0_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>picorv32_core/riscv32_alu_u1/reg_wdata_10_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>865</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.226</td>
<td>0.244</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R25C17[1][B]</td>
<td>picorv32_core/riscv32_alu_u1/op1num_0_s0/CLK</td>
</tr>
<tr>
<td>1.684</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>11</td>
<td>R25C17[1][B]</td>
<td style=" font-weight:bold;">picorv32_core/riscv32_alu_u1/op1num_0_s0/Q</td>
</tr>
<tr>
<td>4.942</td>
<td>3.258</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R16C40[0][A]</td>
<td>picorv32_core/riscv32_alu_u1/op1_add_op2_res_0_s/I0</td>
</tr>
<tr>
<td>5.645</td>
<td>0.703</td>
<td>tINS</td>
<td>FF</td>
<td>22</td>
<td>R16C40[0][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/op1_add_op2_res_0_s/SUM</td>
</tr>
<tr>
<td>9.413</td>
<td>3.768</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R17C14[1][A]</td>
<td>picorv32_core/riscv32_alu_u1/n5982_s38/I1</td>
</tr>
<tr>
<td>10.445</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>10</td>
<td>R17C14[1][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n5982_s38/F</td>
</tr>
<tr>
<td>11.277</td>
<td>0.832</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C12[3][A]</td>
<td>picorv32_core/riscv32_alu_u1/n5924_s50/I3</td>
</tr>
<tr>
<td>11.903</td>
<td>0.626</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>R18C12[3][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n5924_s50/F</td>
</tr>
<tr>
<td>13.366</td>
<td>1.464</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C17[2][B]</td>
<td>picorv32_core/riscv32_alu_u1/n5924_s81/I3</td>
</tr>
<tr>
<td>14.398</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>R18C17[2][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n5924_s81/F</td>
</tr>
<tr>
<td>16.028</td>
<td>1.629</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C29[3][A]</td>
<td>picorv32_core/riscv32_alu_u1/n5956_s47/I2</td>
</tr>
<tr>
<td>16.850</td>
<td>0.822</td>
<td>tINS</td>
<td>FF</td>
<td>8</td>
<td>R18C29[3][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n5956_s47/F</td>
</tr>
<tr>
<td>18.671</td>
<td>1.822</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R14C23[2][A]</td>
<td>picorv32_core/riscv32_alu_u1/n5966_s35/I0</td>
</tr>
<tr>
<td>19.697</td>
<td>1.026</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R14C23[2][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n5966_s35/F</td>
</tr>
<tr>
<td>20.116</td>
<td>0.419</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R14C24[0][A]</td>
<td>picorv32_core/riscv32_alu_u1/n5966_s33/I1</td>
</tr>
<tr>
<td>20.938</td>
<td>0.822</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R14C24[0][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n5966_s33/F</td>
</tr>
<tr>
<td>20.938</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R14C24[0][A]</td>
<td style=" font-weight:bold;">picorv32_core/riscv32_alu_u1/reg_wdata_10_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>20.000</td>
<td>20.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>20.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>865</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>21.226</td>
<td>0.244</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R14C24[0][A]</td>
<td>picorv32_core/riscv32_alu_u1/reg_wdata_10_s0/CLK</td>
</tr>
<tr>
<td>20.826</td>
<td>-0.400</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R14C24[0][A]</td>
<td>picorv32_core/riscv32_alu_u1/reg_wdata_10_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>20.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>8</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.982, 80.100%; route: 0.244, 19.900%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 6.063, 30.757%; route: 13.191, 66.918%; tC2Q: 0.458, 2.325%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.982, 80.100%; route: 0.244, 19.900%</td>
</tr>
</table>
<h3>Path19</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-0.110</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>20.935</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>20.826</td>
</tr>
<tr>
<td class="label">From</td>
<td>picorv32_core/riscv32_alu_u1/instruction_reg_1_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>picorv32_core/riscv32_alu_u1/mret_reg_24_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>865</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.226</td>
<td>0.244</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R14C18[1][B]</td>
<td>picorv32_core/riscv32_alu_u1/instruction_reg_1_s0/CLK</td>
</tr>
<tr>
<td>1.684</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>5</td>
<td>R14C18[1][B]</td>
<td style=" font-weight:bold;">picorv32_core/riscv32_alu_u1/instruction_reg_1_s0/Q</td>
</tr>
<tr>
<td>3.794</td>
<td>2.109</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R23C28[3][A]</td>
<td>picorv32_core/riscv32_alu_u1/reg_waddr_4_s4/I3</td>
</tr>
<tr>
<td>4.616</td>
<td>0.822</td>
<td>tINS</td>
<td>FF</td>
<td>22</td>
<td>R23C28[3][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/reg_waddr_4_s4/F</td>
</tr>
<tr>
<td>5.965</td>
<td>1.349</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R21C31[3][A]</td>
<td>picorv32_core/riscv32_alu_u1/irq_reg_29_s9/I3</td>
</tr>
<tr>
<td>6.591</td>
<td>0.626</td>
<td>tINS</td>
<td>FF</td>
<td>14</td>
<td>R21C31[3][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/irq_reg_29_s9/F</td>
</tr>
<tr>
<td>8.392</td>
<td>1.801</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R16C32[1][B]</td>
<td>picorv32_core/riscv32_alu_u1/irq_reg_29_s10/I3</td>
</tr>
<tr>
<td>9.018</td>
<td>0.626</td>
<td>tINS</td>
<td>FF</td>
<td>16</td>
<td>R16C32[1][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/irq_reg_29_s10/F</td>
</tr>
<tr>
<td>10.994</td>
<td>1.976</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R7C23[2][A]</td>
<td>picorv32_core/riscv32_alu_u1/n6954_s14/I2</td>
</tr>
<tr>
<td>12.093</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>23</td>
<td>R7C23[2][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n6954_s14/F</td>
</tr>
<tr>
<td>14.588</td>
<td>2.495</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R11C40[2][A]</td>
<td>picorv32_core/riscv32_alu_u1/n6820_s15/I0</td>
</tr>
<tr>
<td>15.410</td>
<td>0.822</td>
<td>tINS</td>
<td>FF</td>
<td>17</td>
<td>R11C40[2][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n6820_s15/F</td>
</tr>
<tr>
<td>18.866</td>
<td>3.456</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R20C18[3][B]</td>
<td>picorv32_core/riscv32_alu_u1/n6776_s15/I2</td>
</tr>
<tr>
<td>19.898</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R20C18[3][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n6776_s15/F</td>
</tr>
<tr>
<td>19.903</td>
<td>0.005</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R20C18[0][B]</td>
<td>picorv32_core/riscv32_alu_u1/n6776_s12/I2</td>
</tr>
<tr>
<td>20.935</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R20C18[0][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n6776_s12/F</td>
</tr>
<tr>
<td>20.935</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R20C18[0][B]</td>
<td style=" font-weight:bold;">picorv32_core/riscv32_alu_u1/mret_reg_24_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>20.000</td>
<td>20.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>20.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>865</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>21.226</td>
<td>0.244</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C18[0][B]</td>
<td>picorv32_core/riscv32_alu_u1/mret_reg_24_s0/CLK</td>
</tr>
<tr>
<td>20.826</td>
<td>-0.400</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R20C18[0][B]</td>
<td>picorv32_core/riscv32_alu_u1/mret_reg_24_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>20.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>8</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.982, 80.100%; route: 0.244, 19.900%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 6.059, 30.741%; route: 13.192, 66.933%; tC2Q: 0.458, 2.325%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.982, 80.100%; route: 0.244, 19.900%</td>
</tr>
</table>
<h3>Path20</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-0.099</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>20.925</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>20.826</td>
</tr>
<tr>
<td class="label">From</td>
<td>picorv32_core/riscv32_alu_u1/op1num_1_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>picorv32_core/riscv32_alu_u1/risc_v_pc_27_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>865</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.226</td>
<td>0.244</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R14C15[0][A]</td>
<td>picorv32_core/riscv32_alu_u1/op1num_1_s0/CLK</td>
</tr>
<tr>
<td>1.684</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>12</td>
<td>R14C15[0][A]</td>
<td style=" font-weight:bold;">picorv32_core/riscv32_alu_u1/op1num_1_s0/Q</td>
</tr>
<tr>
<td>4.478</td>
<td>2.793</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C31[1][A]</td>
<td>picorv32_core/riscv32_alu_u1/n246_s64/I0</td>
</tr>
<tr>
<td>5.436</td>
<td>0.958</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C31[1][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n246_s64/COUT</td>
</tr>
<tr>
<td>5.436</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C31[1][B]</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s65/CIN</td>
</tr>
<tr>
<td>5.493</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C31[1][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s65/COUT</td>
</tr>
<tr>
<td>5.493</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C31[2][A]</td>
<td>picorv32_core/riscv32_alu_u1/n246_s65/CIN</td>
</tr>
<tr>
<td>5.550</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C31[2][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n246_s65/COUT</td>
</tr>
<tr>
<td>5.550</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C31[2][B]</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s66/CIN</td>
</tr>
<tr>
<td>5.607</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C31[2][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s66/COUT</td>
</tr>
<tr>
<td>5.607</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C32[0][A]</td>
<td>picorv32_core/riscv32_alu_u1/n246_s66/CIN</td>
</tr>
<tr>
<td>5.664</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C32[0][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n246_s66/COUT</td>
</tr>
<tr>
<td>5.664</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C32[0][B]</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s67/CIN</td>
</tr>
<tr>
<td>5.721</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C32[0][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s67/COUT</td>
</tr>
<tr>
<td>5.721</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C32[1][A]</td>
<td>picorv32_core/riscv32_alu_u1/n246_s67/CIN</td>
</tr>
<tr>
<td>5.778</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C32[1][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n246_s67/COUT</td>
</tr>
<tr>
<td>5.778</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C32[1][B]</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s68/CIN</td>
</tr>
<tr>
<td>5.835</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C32[1][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s68/COUT</td>
</tr>
<tr>
<td>5.835</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C32[2][A]</td>
<td>picorv32_core/riscv32_alu_u1/n246_s68/CIN</td>
</tr>
<tr>
<td>5.892</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C32[2][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n246_s68/COUT</td>
</tr>
<tr>
<td>5.892</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C32[2][B]</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s69/CIN</td>
</tr>
<tr>
<td>5.949</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C32[2][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s69/COUT</td>
</tr>
<tr>
<td>5.949</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C33[0][A]</td>
<td>picorv32_core/riscv32_alu_u1/n246_s69/CIN</td>
</tr>
<tr>
<td>6.006</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C33[0][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n246_s69/COUT</td>
</tr>
<tr>
<td>6.006</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C33[0][B]</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s70/CIN</td>
</tr>
<tr>
<td>6.063</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C33[0][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s70/COUT</td>
</tr>
<tr>
<td>6.063</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C33[1][A]</td>
<td>picorv32_core/riscv32_alu_u1/n246_s70/CIN</td>
</tr>
<tr>
<td>6.120</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C33[1][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n246_s70/COUT</td>
</tr>
<tr>
<td>6.120</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C33[1][B]</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s71/CIN</td>
</tr>
<tr>
<td>6.177</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C33[1][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s71/COUT</td>
</tr>
<tr>
<td>6.177</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C33[2][A]</td>
<td>picorv32_core/riscv32_alu_u1/n246_s71/CIN</td>
</tr>
<tr>
<td>6.234</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C33[2][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n246_s71/COUT</td>
</tr>
<tr>
<td>6.234</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C33[2][B]</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s72/CIN</td>
</tr>
<tr>
<td>6.291</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C33[2][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s72/COUT</td>
</tr>
<tr>
<td>6.291</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C34[0][A]</td>
<td>picorv32_core/riscv32_alu_u1/n246_s72/CIN</td>
</tr>
<tr>
<td>6.348</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C34[0][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n246_s72/COUT</td>
</tr>
<tr>
<td>6.348</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C34[0][B]</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s73/CIN</td>
</tr>
<tr>
<td>6.405</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C34[0][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s73/COUT</td>
</tr>
<tr>
<td>6.405</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C34[1][A]</td>
<td>picorv32_core/riscv32_alu_u1/n246_s73/CIN</td>
</tr>
<tr>
<td>6.462</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C34[1][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n246_s73/COUT</td>
</tr>
<tr>
<td>6.462</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C34[1][B]</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s74/CIN</td>
</tr>
<tr>
<td>6.519</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C34[1][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s74/COUT</td>
</tr>
<tr>
<td>6.519</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C34[2][A]</td>
<td>picorv32_core/riscv32_alu_u1/n246_s74/CIN</td>
</tr>
<tr>
<td>6.576</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C34[2][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n246_s74/COUT</td>
</tr>
<tr>
<td>6.576</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C34[2][B]</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s75/CIN</td>
</tr>
<tr>
<td>6.633</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C34[2][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s75/COUT</td>
</tr>
<tr>
<td>6.633</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C35[0][A]</td>
<td>picorv32_core/riscv32_alu_u1/n246_s75/CIN</td>
</tr>
<tr>
<td>6.690</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C35[0][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n246_s75/COUT</td>
</tr>
<tr>
<td>6.690</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C35[0][B]</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s76/CIN</td>
</tr>
<tr>
<td>6.747</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C35[0][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s76/COUT</td>
</tr>
<tr>
<td>6.747</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C35[1][A]</td>
<td>picorv32_core/riscv32_alu_u1/n246_s76/CIN</td>
</tr>
<tr>
<td>6.804</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C35[1][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n246_s76/COUT</td>
</tr>
<tr>
<td>6.804</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C35[1][B]</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s77/CIN</td>
</tr>
<tr>
<td>6.861</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C35[1][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s77/COUT</td>
</tr>
<tr>
<td>6.861</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C35[2][A]</td>
<td>picorv32_core/riscv32_alu_u1/n246_s77/CIN</td>
</tr>
<tr>
<td>6.918</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C35[2][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n246_s77/COUT</td>
</tr>
<tr>
<td>6.918</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C35[2][B]</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s78/CIN</td>
</tr>
<tr>
<td>6.975</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C35[2][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s78/COUT</td>
</tr>
<tr>
<td>6.975</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C36[0][A]</td>
<td>picorv32_core/riscv32_alu_u1/n246_s78/CIN</td>
</tr>
<tr>
<td>7.032</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C36[0][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n246_s78/COUT</td>
</tr>
<tr>
<td>8.569</td>
<td>1.538</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R22C34[3][B]</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s80/I2</td>
</tr>
<tr>
<td>9.601</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>R22C34[3][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s80/F</td>
</tr>
<tr>
<td>10.416</td>
<td>0.814</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R21C32[3][B]</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_unsigned_s1/I2</td>
</tr>
<tr>
<td>11.515</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>R21C32[3][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/op1_ge_op2_unsigned_s1/F</td>
</tr>
<tr>
<td>11.526</td>
<td>0.011</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R21C32[0][B]</td>
<td>picorv32_core/riscv32_alu_u1/n1673_s10/I3</td>
</tr>
<tr>
<td>12.558</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R21C32[0][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n1673_s10/F</td>
</tr>
<tr>
<td>12.563</td>
<td>0.005</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R21C32[1][B]</td>
<td>picorv32_core/riscv32_alu_u1/n6826_s22/I0</td>
</tr>
<tr>
<td>13.624</td>
<td>1.061</td>
<td>tINS</td>
<td>FR</td>
<td>2</td>
<td>R21C32[1][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n6826_s22/F</td>
</tr>
<tr>
<td>14.045</td>
<td>0.421</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C31[0][B]</td>
<td>picorv32_core/riscv32_alu_u1/n6826_s19/I0</td>
</tr>
<tr>
<td>14.671</td>
<td>0.626</td>
<td>tINS</td>
<td>RF</td>
<td>31</td>
<td>R21C31[0][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n6826_s19/F</td>
</tr>
<tr>
<td>17.200</td>
<td>2.529</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R8C39[1][B]</td>
<td>picorv32_core/riscv32_alu_u1/n6834_s11/I0</td>
</tr>
<tr>
<td>18.232</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R8C39[1][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n6834_s11/F</td>
</tr>
<tr>
<td>18.722</td>
<td>0.490</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R6C39[1][B]</td>
<td>picorv32_core/riscv32_alu_u1/n6834_s8/I2</td>
</tr>
<tr>
<td>19.821</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R6C39[1][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n6834_s8/F</td>
</tr>
<tr>
<td>19.826</td>
<td>0.005</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R6C39[0][A]</td>
<td>picorv32_core/riscv32_alu_u1/n6834_s7/I1</td>
</tr>
<tr>
<td>20.925</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R6C39[0][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n6834_s7/F</td>
</tr>
<tr>
<td>20.925</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R6C39[0][A]</td>
<td style=" font-weight:bold;">picorv32_core/riscv32_alu_u1/risc_v_pc_27_s1/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>20.000</td>
<td>20.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>20.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>865</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>21.226</td>
<td>0.244</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R6C39[0][A]</td>
<td>picorv32_core/riscv32_alu_u1/risc_v_pc_27_s1/CLK</td>
</tr>
<tr>
<td>20.826</td>
<td>-0.400</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R6C39[0][A]</td>
<td>picorv32_core/riscv32_alu_u1/risc_v_pc_27_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>20.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>14</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.982, 80.100%; route: 0.244, 19.900%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 10.634, 53.981%; route: 8.607, 43.692%; tC2Q: 0.458, 2.327%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.982, 80.100%; route: 0.244, 19.900%</td>
</tr>
</table>
<h3>Path21</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-0.089</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>20.914</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>20.826</td>
</tr>
<tr>
<td class="label">From</td>
<td>picorv32_core/riscv32_alu_u1/op1num_1_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>picorv32_core/riscv32_alu_u1/risc_v_pc_10_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>865</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.226</td>
<td>0.244</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R14C15[0][A]</td>
<td>picorv32_core/riscv32_alu_u1/op1num_1_s0/CLK</td>
</tr>
<tr>
<td>1.684</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>12</td>
<td>R14C15[0][A]</td>
<td style=" font-weight:bold;">picorv32_core/riscv32_alu_u1/op1num_1_s0/Q</td>
</tr>
<tr>
<td>4.478</td>
<td>2.793</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C31[1][A]</td>
<td>picorv32_core/riscv32_alu_u1/n246_s64/I0</td>
</tr>
<tr>
<td>5.436</td>
<td>0.958</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C31[1][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n246_s64/COUT</td>
</tr>
<tr>
<td>5.436</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C31[1][B]</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s65/CIN</td>
</tr>
<tr>
<td>5.493</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C31[1][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s65/COUT</td>
</tr>
<tr>
<td>5.493</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C31[2][A]</td>
<td>picorv32_core/riscv32_alu_u1/n246_s65/CIN</td>
</tr>
<tr>
<td>5.550</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C31[2][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n246_s65/COUT</td>
</tr>
<tr>
<td>5.550</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C31[2][B]</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s66/CIN</td>
</tr>
<tr>
<td>5.607</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C31[2][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s66/COUT</td>
</tr>
<tr>
<td>5.607</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C32[0][A]</td>
<td>picorv32_core/riscv32_alu_u1/n246_s66/CIN</td>
</tr>
<tr>
<td>5.664</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C32[0][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n246_s66/COUT</td>
</tr>
<tr>
<td>5.664</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C32[0][B]</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s67/CIN</td>
</tr>
<tr>
<td>5.721</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C32[0][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s67/COUT</td>
</tr>
<tr>
<td>5.721</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C32[1][A]</td>
<td>picorv32_core/riscv32_alu_u1/n246_s67/CIN</td>
</tr>
<tr>
<td>5.778</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C32[1][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n246_s67/COUT</td>
</tr>
<tr>
<td>5.778</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C32[1][B]</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s68/CIN</td>
</tr>
<tr>
<td>5.835</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C32[1][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s68/COUT</td>
</tr>
<tr>
<td>5.835</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C32[2][A]</td>
<td>picorv32_core/riscv32_alu_u1/n246_s68/CIN</td>
</tr>
<tr>
<td>5.892</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C32[2][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n246_s68/COUT</td>
</tr>
<tr>
<td>5.892</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C32[2][B]</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s69/CIN</td>
</tr>
<tr>
<td>5.949</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C32[2][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s69/COUT</td>
</tr>
<tr>
<td>5.949</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C33[0][A]</td>
<td>picorv32_core/riscv32_alu_u1/n246_s69/CIN</td>
</tr>
<tr>
<td>6.006</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C33[0][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n246_s69/COUT</td>
</tr>
<tr>
<td>6.006</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C33[0][B]</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s70/CIN</td>
</tr>
<tr>
<td>6.063</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C33[0][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s70/COUT</td>
</tr>
<tr>
<td>6.063</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C33[1][A]</td>
<td>picorv32_core/riscv32_alu_u1/n246_s70/CIN</td>
</tr>
<tr>
<td>6.120</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C33[1][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n246_s70/COUT</td>
</tr>
<tr>
<td>6.120</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C33[1][B]</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s71/CIN</td>
</tr>
<tr>
<td>6.177</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C33[1][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s71/COUT</td>
</tr>
<tr>
<td>6.177</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C33[2][A]</td>
<td>picorv32_core/riscv32_alu_u1/n246_s71/CIN</td>
</tr>
<tr>
<td>6.234</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C33[2][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n246_s71/COUT</td>
</tr>
<tr>
<td>6.234</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C33[2][B]</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s72/CIN</td>
</tr>
<tr>
<td>6.291</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C33[2][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s72/COUT</td>
</tr>
<tr>
<td>6.291</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C34[0][A]</td>
<td>picorv32_core/riscv32_alu_u1/n246_s72/CIN</td>
</tr>
<tr>
<td>6.348</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C34[0][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n246_s72/COUT</td>
</tr>
<tr>
<td>6.348</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C34[0][B]</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s73/CIN</td>
</tr>
<tr>
<td>6.405</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C34[0][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s73/COUT</td>
</tr>
<tr>
<td>6.405</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C34[1][A]</td>
<td>picorv32_core/riscv32_alu_u1/n246_s73/CIN</td>
</tr>
<tr>
<td>6.462</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C34[1][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n246_s73/COUT</td>
</tr>
<tr>
<td>6.462</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C34[1][B]</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s74/CIN</td>
</tr>
<tr>
<td>6.519</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C34[1][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s74/COUT</td>
</tr>
<tr>
<td>6.519</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C34[2][A]</td>
<td>picorv32_core/riscv32_alu_u1/n246_s74/CIN</td>
</tr>
<tr>
<td>6.576</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C34[2][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n246_s74/COUT</td>
</tr>
<tr>
<td>6.576</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C34[2][B]</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s75/CIN</td>
</tr>
<tr>
<td>6.633</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C34[2][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s75/COUT</td>
</tr>
<tr>
<td>6.633</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C35[0][A]</td>
<td>picorv32_core/riscv32_alu_u1/n246_s75/CIN</td>
</tr>
<tr>
<td>6.690</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C35[0][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n246_s75/COUT</td>
</tr>
<tr>
<td>6.690</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C35[0][B]</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s76/CIN</td>
</tr>
<tr>
<td>6.747</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C35[0][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s76/COUT</td>
</tr>
<tr>
<td>6.747</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C35[1][A]</td>
<td>picorv32_core/riscv32_alu_u1/n246_s76/CIN</td>
</tr>
<tr>
<td>6.804</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C35[1][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n246_s76/COUT</td>
</tr>
<tr>
<td>6.804</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C35[1][B]</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s77/CIN</td>
</tr>
<tr>
<td>6.861</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C35[1][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s77/COUT</td>
</tr>
<tr>
<td>6.861</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C35[2][A]</td>
<td>picorv32_core/riscv32_alu_u1/n246_s77/CIN</td>
</tr>
<tr>
<td>6.918</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C35[2][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n246_s77/COUT</td>
</tr>
<tr>
<td>6.918</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C35[2][B]</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s78/CIN</td>
</tr>
<tr>
<td>6.975</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C35[2][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s78/COUT</td>
</tr>
<tr>
<td>6.975</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C36[0][A]</td>
<td>picorv32_core/riscv32_alu_u1/n246_s78/CIN</td>
</tr>
<tr>
<td>7.032</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C36[0][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n246_s78/COUT</td>
</tr>
<tr>
<td>8.569</td>
<td>1.538</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R22C34[3][B]</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s80/I2</td>
</tr>
<tr>
<td>9.601</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>R22C34[3][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s80/F</td>
</tr>
<tr>
<td>10.416</td>
<td>0.814</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R21C32[3][B]</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_unsigned_s1/I2</td>
</tr>
<tr>
<td>11.515</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>R21C32[3][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/op1_ge_op2_unsigned_s1/F</td>
</tr>
<tr>
<td>11.526</td>
<td>0.011</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R21C32[0][B]</td>
<td>picorv32_core/riscv32_alu_u1/n1673_s10/I3</td>
</tr>
<tr>
<td>12.558</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R21C32[0][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n1673_s10/F</td>
</tr>
<tr>
<td>12.563</td>
<td>0.005</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R21C32[1][B]</td>
<td>picorv32_core/riscv32_alu_u1/n6826_s22/I0</td>
</tr>
<tr>
<td>13.624</td>
<td>1.061</td>
<td>tINS</td>
<td>FR</td>
<td>2</td>
<td>R21C32[1][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n6826_s22/F</td>
</tr>
<tr>
<td>14.045</td>
<td>0.421</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C31[0][B]</td>
<td>picorv32_core/riscv32_alu_u1/n6826_s19/I0</td>
</tr>
<tr>
<td>14.671</td>
<td>0.626</td>
<td>tINS</td>
<td>RF</td>
<td>31</td>
<td>R21C31[0][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n6826_s19/F</td>
</tr>
<tr>
<td>16.532</td>
<td>1.861</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R11C23[1][B]</td>
<td>picorv32_core/riscv32_alu_u1/n6868_s12/I2</td>
</tr>
<tr>
<td>17.631</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R11C23[1][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n6868_s12/F</td>
</tr>
<tr>
<td>18.436</td>
<td>0.804</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R8C23[3][B]</td>
<td>picorv32_core/riscv32_alu_u1/n6868_s8/I3</td>
</tr>
<tr>
<td>19.468</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R8C23[3][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n6868_s8/F</td>
</tr>
<tr>
<td>20.288</td>
<td>0.821</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R8C21[1][B]</td>
<td>picorv32_core/riscv32_alu_u1/n6868_s7/I0</td>
</tr>
<tr>
<td>20.914</td>
<td>0.626</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R8C21[1][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n6868_s7/F</td>
</tr>
<tr>
<td>20.914</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R8C21[1][B]</td>
<td style=" font-weight:bold;">picorv32_core/riscv32_alu_u1/risc_v_pc_10_s1/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>20.000</td>
<td>20.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>20.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>865</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>21.226</td>
<td>0.244</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R8C21[1][B]</td>
<td>picorv32_core/riscv32_alu_u1/risc_v_pc_10_s1/CLK</td>
</tr>
<tr>
<td>20.826</td>
<td>-0.400</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R8C21[1][B]</td>
<td>picorv32_core/riscv32_alu_u1/risc_v_pc_10_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>20.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>14</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.982, 80.100%; route: 0.244, 19.900%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 10.161, 51.608%; route: 9.069, 46.064%; tC2Q: 0.458, 2.328%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.982, 80.100%; route: 0.244, 19.900%</td>
</tr>
</table>
<h3>Path22</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-0.080</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>20.905</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>20.826</td>
</tr>
<tr>
<td class="label">From</td>
<td>picorv32_core/riscv32_alu_u1/op1num_1_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>picorv32_core/riscv32_alu_u1/risc_v_pc_4_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>865</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.226</td>
<td>0.244</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R14C15[0][A]</td>
<td>picorv32_core/riscv32_alu_u1/op1num_1_s0/CLK</td>
</tr>
<tr>
<td>1.684</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>12</td>
<td>R14C15[0][A]</td>
<td style=" font-weight:bold;">picorv32_core/riscv32_alu_u1/op1num_1_s0/Q</td>
</tr>
<tr>
<td>4.478</td>
<td>2.793</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C31[1][A]</td>
<td>picorv32_core/riscv32_alu_u1/n246_s64/I0</td>
</tr>
<tr>
<td>5.436</td>
<td>0.958</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C31[1][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n246_s64/COUT</td>
</tr>
<tr>
<td>5.436</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C31[1][B]</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s65/CIN</td>
</tr>
<tr>
<td>5.493</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C31[1][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s65/COUT</td>
</tr>
<tr>
<td>5.493</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C31[2][A]</td>
<td>picorv32_core/riscv32_alu_u1/n246_s65/CIN</td>
</tr>
<tr>
<td>5.550</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C31[2][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n246_s65/COUT</td>
</tr>
<tr>
<td>5.550</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C31[2][B]</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s66/CIN</td>
</tr>
<tr>
<td>5.607</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C31[2][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s66/COUT</td>
</tr>
<tr>
<td>5.607</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C32[0][A]</td>
<td>picorv32_core/riscv32_alu_u1/n246_s66/CIN</td>
</tr>
<tr>
<td>5.664</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C32[0][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n246_s66/COUT</td>
</tr>
<tr>
<td>5.664</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C32[0][B]</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s67/CIN</td>
</tr>
<tr>
<td>5.721</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C32[0][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s67/COUT</td>
</tr>
<tr>
<td>5.721</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C32[1][A]</td>
<td>picorv32_core/riscv32_alu_u1/n246_s67/CIN</td>
</tr>
<tr>
<td>5.778</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C32[1][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n246_s67/COUT</td>
</tr>
<tr>
<td>5.778</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C32[1][B]</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s68/CIN</td>
</tr>
<tr>
<td>5.835</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C32[1][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s68/COUT</td>
</tr>
<tr>
<td>5.835</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C32[2][A]</td>
<td>picorv32_core/riscv32_alu_u1/n246_s68/CIN</td>
</tr>
<tr>
<td>5.892</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C32[2][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n246_s68/COUT</td>
</tr>
<tr>
<td>5.892</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C32[2][B]</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s69/CIN</td>
</tr>
<tr>
<td>5.949</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C32[2][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s69/COUT</td>
</tr>
<tr>
<td>5.949</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C33[0][A]</td>
<td>picorv32_core/riscv32_alu_u1/n246_s69/CIN</td>
</tr>
<tr>
<td>6.006</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C33[0][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n246_s69/COUT</td>
</tr>
<tr>
<td>6.006</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C33[0][B]</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s70/CIN</td>
</tr>
<tr>
<td>6.063</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C33[0][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s70/COUT</td>
</tr>
<tr>
<td>6.063</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C33[1][A]</td>
<td>picorv32_core/riscv32_alu_u1/n246_s70/CIN</td>
</tr>
<tr>
<td>6.120</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C33[1][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n246_s70/COUT</td>
</tr>
<tr>
<td>6.120</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C33[1][B]</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s71/CIN</td>
</tr>
<tr>
<td>6.177</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C33[1][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s71/COUT</td>
</tr>
<tr>
<td>6.177</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C33[2][A]</td>
<td>picorv32_core/riscv32_alu_u1/n246_s71/CIN</td>
</tr>
<tr>
<td>6.234</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C33[2][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n246_s71/COUT</td>
</tr>
<tr>
<td>6.234</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C33[2][B]</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s72/CIN</td>
</tr>
<tr>
<td>6.291</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C33[2][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s72/COUT</td>
</tr>
<tr>
<td>6.291</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C34[0][A]</td>
<td>picorv32_core/riscv32_alu_u1/n246_s72/CIN</td>
</tr>
<tr>
<td>6.348</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C34[0][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n246_s72/COUT</td>
</tr>
<tr>
<td>6.348</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C34[0][B]</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s73/CIN</td>
</tr>
<tr>
<td>6.405</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C34[0][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s73/COUT</td>
</tr>
<tr>
<td>6.405</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C34[1][A]</td>
<td>picorv32_core/riscv32_alu_u1/n246_s73/CIN</td>
</tr>
<tr>
<td>6.462</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C34[1][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n246_s73/COUT</td>
</tr>
<tr>
<td>6.462</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C34[1][B]</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s74/CIN</td>
</tr>
<tr>
<td>6.519</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C34[1][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s74/COUT</td>
</tr>
<tr>
<td>6.519</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C34[2][A]</td>
<td>picorv32_core/riscv32_alu_u1/n246_s74/CIN</td>
</tr>
<tr>
<td>6.576</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C34[2][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n246_s74/COUT</td>
</tr>
<tr>
<td>6.576</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C34[2][B]</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s75/CIN</td>
</tr>
<tr>
<td>6.633</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C34[2][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s75/COUT</td>
</tr>
<tr>
<td>6.633</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C35[0][A]</td>
<td>picorv32_core/riscv32_alu_u1/n246_s75/CIN</td>
</tr>
<tr>
<td>6.690</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C35[0][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n246_s75/COUT</td>
</tr>
<tr>
<td>6.690</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C35[0][B]</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s76/CIN</td>
</tr>
<tr>
<td>6.747</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C35[0][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s76/COUT</td>
</tr>
<tr>
<td>6.747</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C35[1][A]</td>
<td>picorv32_core/riscv32_alu_u1/n246_s76/CIN</td>
</tr>
<tr>
<td>6.804</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C35[1][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n246_s76/COUT</td>
</tr>
<tr>
<td>6.804</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C35[1][B]</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s77/CIN</td>
</tr>
<tr>
<td>6.861</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C35[1][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s77/COUT</td>
</tr>
<tr>
<td>6.861</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C35[2][A]</td>
<td>picorv32_core/riscv32_alu_u1/n246_s77/CIN</td>
</tr>
<tr>
<td>6.918</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C35[2][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n246_s77/COUT</td>
</tr>
<tr>
<td>6.918</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C35[2][B]</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s78/CIN</td>
</tr>
<tr>
<td>6.975</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C35[2][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s78/COUT</td>
</tr>
<tr>
<td>6.975</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C36[0][A]</td>
<td>picorv32_core/riscv32_alu_u1/n246_s78/CIN</td>
</tr>
<tr>
<td>7.032</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C36[0][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n246_s78/COUT</td>
</tr>
<tr>
<td>8.569</td>
<td>1.538</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R22C34[3][B]</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s80/I2</td>
</tr>
<tr>
<td>9.601</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>R22C34[3][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s80/F</td>
</tr>
<tr>
<td>10.416</td>
<td>0.814</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R21C32[3][B]</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_unsigned_s1/I2</td>
</tr>
<tr>
<td>11.515</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>R21C32[3][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/op1_ge_op2_unsigned_s1/F</td>
</tr>
<tr>
<td>11.526</td>
<td>0.011</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R21C32[0][B]</td>
<td>picorv32_core/riscv32_alu_u1/n1673_s10/I3</td>
</tr>
<tr>
<td>12.558</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R21C32[0][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n1673_s10/F</td>
</tr>
<tr>
<td>12.563</td>
<td>0.005</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R21C32[1][B]</td>
<td>picorv32_core/riscv32_alu_u1/n6826_s22/I0</td>
</tr>
<tr>
<td>13.624</td>
<td>1.061</td>
<td>tINS</td>
<td>FR</td>
<td>2</td>
<td>R21C32[1][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n6826_s22/F</td>
</tr>
<tr>
<td>14.045</td>
<td>0.421</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C31[0][B]</td>
<td>picorv32_core/riscv32_alu_u1/n6826_s19/I0</td>
</tr>
<tr>
<td>14.671</td>
<td>0.626</td>
<td>tINS</td>
<td>RF</td>
<td>31</td>
<td>R21C31[0][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n6826_s19/F</td>
</tr>
<tr>
<td>16.658</td>
<td>1.987</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R13C39[1][B]</td>
<td>picorv32_core/riscv32_alu_u1/n6880_s11/I0</td>
</tr>
<tr>
<td>17.690</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R13C39[1][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n6880_s11/F</td>
</tr>
<tr>
<td>17.695</td>
<td>0.005</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R13C39[3][B]</td>
<td>picorv32_core/riscv32_alu_u1/n6880_s8/I2</td>
</tr>
<tr>
<td>18.794</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R13C39[3][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n6880_s8/F</td>
</tr>
<tr>
<td>20.083</td>
<td>1.289</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R11C40[1][B]</td>
<td>picorv32_core/riscv32_alu_u1/n6880_s7/I0</td>
</tr>
<tr>
<td>20.905</td>
<td>0.822</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R11C40[1][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n6880_s7/F</td>
</tr>
<tr>
<td>20.905</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R11C40[1][B]</td>
<td style=" font-weight:bold;">picorv32_core/riscv32_alu_u1/risc_v_pc_4_s1/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>20.000</td>
<td>20.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>20.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>865</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>21.226</td>
<td>0.244</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C40[1][B]</td>
<td>picorv32_core/riscv32_alu_u1/risc_v_pc_4_s1/CLK</td>
</tr>
<tr>
<td>20.826</td>
<td>-0.400</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R11C40[1][B]</td>
<td>picorv32_core/riscv32_alu_u1/risc_v_pc_4_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>20.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>14</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.982, 80.100%; route: 0.244, 19.900%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 10.357, 52.628%; route: 8.864, 45.043%; tC2Q: 0.458, 2.329%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.982, 80.100%; route: 0.244, 19.900%</td>
</tr>
</table>
<h3>Path23</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-0.078</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>20.904</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>20.826</td>
</tr>
<tr>
<td class="label">From</td>
<td>picorv32_core/riscv32_alu_u1/op1num_0_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>picorv32_core/riscv32_alu_u1/reg_wdata_24_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>865</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.226</td>
<td>0.244</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R25C17[1][B]</td>
<td>picorv32_core/riscv32_alu_u1/op1num_0_s0/CLK</td>
</tr>
<tr>
<td>1.684</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>11</td>
<td>R25C17[1][B]</td>
<td style=" font-weight:bold;">picorv32_core/riscv32_alu_u1/op1num_0_s0/Q</td>
</tr>
<tr>
<td>4.948</td>
<td>3.264</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R16C34[0][A]</td>
<td>picorv32_core/riscv32_alu_u1/num1_sub_num2_0_s/I0</td>
</tr>
<tr>
<td>5.906</td>
<td>0.958</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R16C34[0][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/num1_sub_num2_0_s/COUT</td>
</tr>
<tr>
<td>5.906</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R16C34[0][B]</td>
<td>picorv32_core/riscv32_alu_u1/num1_sub_num2_1_s/CIN</td>
</tr>
<tr>
<td>5.963</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R16C34[0][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/num1_sub_num2_1_s/COUT</td>
</tr>
<tr>
<td>5.963</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R16C34[1][A]</td>
<td>picorv32_core/riscv32_alu_u1/num1_sub_num2_2_s/CIN</td>
</tr>
<tr>
<td>6.020</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R16C34[1][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/num1_sub_num2_2_s/COUT</td>
</tr>
<tr>
<td>6.020</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R16C34[1][B]</td>
<td>picorv32_core/riscv32_alu_u1/num1_sub_num2_3_s/CIN</td>
</tr>
<tr>
<td>6.077</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R16C34[1][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/num1_sub_num2_3_s/COUT</td>
</tr>
<tr>
<td>6.077</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R16C34[2][A]</td>
<td>picorv32_core/riscv32_alu_u1/num1_sub_num2_4_s/CIN</td>
</tr>
<tr>
<td>6.134</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R16C34[2][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/num1_sub_num2_4_s/COUT</td>
</tr>
<tr>
<td>6.134</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R16C34[2][B]</td>
<td>picorv32_core/riscv32_alu_u1/num1_sub_num2_5_s/CIN</td>
</tr>
<tr>
<td>6.191</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R16C34[2][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/num1_sub_num2_5_s/COUT</td>
</tr>
<tr>
<td>6.191</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R16C35[0][A]</td>
<td>picorv32_core/riscv32_alu_u1/num1_sub_num2_6_s/CIN</td>
</tr>
<tr>
<td>6.248</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R16C35[0][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/num1_sub_num2_6_s/COUT</td>
</tr>
<tr>
<td>6.248</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R16C35[0][B]</td>
<td>picorv32_core/riscv32_alu_u1/num1_sub_num2_7_s/CIN</td>
</tr>
<tr>
<td>6.305</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R16C35[0][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/num1_sub_num2_7_s/COUT</td>
</tr>
<tr>
<td>6.305</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R16C35[1][A]</td>
<td>picorv32_core/riscv32_alu_u1/num1_sub_num2_8_s/CIN</td>
</tr>
<tr>
<td>6.362</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R16C35[1][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/num1_sub_num2_8_s/COUT</td>
</tr>
<tr>
<td>6.362</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R16C35[1][B]</td>
<td>picorv32_core/riscv32_alu_u1/num1_sub_num2_9_s/CIN</td>
</tr>
<tr>
<td>6.419</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R16C35[1][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/num1_sub_num2_9_s/COUT</td>
</tr>
<tr>
<td>6.419</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R16C35[2][A]</td>
<td>picorv32_core/riscv32_alu_u1/num1_sub_num2_10_s/CIN</td>
</tr>
<tr>
<td>6.476</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R16C35[2][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/num1_sub_num2_10_s/COUT</td>
</tr>
<tr>
<td>6.476</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R16C35[2][B]</td>
<td>picorv32_core/riscv32_alu_u1/num1_sub_num2_11_s/CIN</td>
</tr>
<tr>
<td>6.533</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R16C35[2][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/num1_sub_num2_11_s/COUT</td>
</tr>
<tr>
<td>6.533</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R16C36[0][A]</td>
<td>picorv32_core/riscv32_alu_u1/num1_sub_num2_12_s/CIN</td>
</tr>
<tr>
<td>6.590</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R16C36[0][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/num1_sub_num2_12_s/COUT</td>
</tr>
<tr>
<td>6.590</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R16C36[0][B]</td>
<td>picorv32_core/riscv32_alu_u1/num1_sub_num2_13_s/CIN</td>
</tr>
<tr>
<td>6.647</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R16C36[0][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/num1_sub_num2_13_s/COUT</td>
</tr>
<tr>
<td>6.647</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R16C36[1][A]</td>
<td>picorv32_core/riscv32_alu_u1/num1_sub_num2_14_s/CIN</td>
</tr>
<tr>
<td>6.704</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R16C36[1][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/num1_sub_num2_14_s/COUT</td>
</tr>
<tr>
<td>6.704</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R16C36[1][B]</td>
<td>picorv32_core/riscv32_alu_u1/num1_sub_num2_15_s/CIN</td>
</tr>
<tr>
<td>6.761</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R16C36[1][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/num1_sub_num2_15_s/COUT</td>
</tr>
<tr>
<td>6.761</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R16C36[2][A]</td>
<td>picorv32_core/riscv32_alu_u1/num1_sub_num2_16_s/CIN</td>
</tr>
<tr>
<td>6.818</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R16C36[2][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/num1_sub_num2_16_s/COUT</td>
</tr>
<tr>
<td>6.818</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R16C36[2][B]</td>
<td>picorv32_core/riscv32_alu_u1/num1_sub_num2_17_s/CIN</td>
</tr>
<tr>
<td>6.875</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R16C36[2][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/num1_sub_num2_17_s/COUT</td>
</tr>
<tr>
<td>6.875</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R16C37[0][A]</td>
<td>picorv32_core/riscv32_alu_u1/num1_sub_num2_18_s/CIN</td>
</tr>
<tr>
<td>6.932</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R16C37[0][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/num1_sub_num2_18_s/COUT</td>
</tr>
<tr>
<td>6.932</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R16C37[0][B]</td>
<td>picorv32_core/riscv32_alu_u1/num1_sub_num2_19_s/CIN</td>
</tr>
<tr>
<td>6.989</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R16C37[0][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/num1_sub_num2_19_s/COUT</td>
</tr>
<tr>
<td>6.989</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R16C37[1][A]</td>
<td>picorv32_core/riscv32_alu_u1/num1_sub_num2_20_s/CIN</td>
</tr>
<tr>
<td>7.046</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R16C37[1][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/num1_sub_num2_20_s/COUT</td>
</tr>
<tr>
<td>7.046</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R16C37[1][B]</td>
<td>picorv32_core/riscv32_alu_u1/num1_sub_num2_21_s/CIN</td>
</tr>
<tr>
<td>7.103</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R16C37[1][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/num1_sub_num2_21_s/COUT</td>
</tr>
<tr>
<td>7.103</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R16C37[2][A]</td>
<td>picorv32_core/riscv32_alu_u1/num1_sub_num2_22_s/CIN</td>
</tr>
<tr>
<td>7.160</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R16C37[2][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/num1_sub_num2_22_s/COUT</td>
</tr>
<tr>
<td>7.160</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R16C37[2][B]</td>
<td>picorv32_core/riscv32_alu_u1/num1_sub_num2_23_s/CIN</td>
</tr>
<tr>
<td>7.217</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R16C37[2][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/num1_sub_num2_23_s/COUT</td>
</tr>
<tr>
<td>7.217</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R16C38[0][A]</td>
<td>picorv32_core/riscv32_alu_u1/num1_sub_num2_24_s/CIN</td>
</tr>
<tr>
<td>7.780</td>
<td>0.563</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R16C38[0][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/num1_sub_num2_24_s/SUM</td>
</tr>
<tr>
<td>11.336</td>
<td>3.556</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R16C22[1][A]</td>
<td>picorv32_core/riscv32_alu_u1/n5938_s56/I0</td>
</tr>
<tr>
<td>12.368</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R16C22[1][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n5938_s56/F</td>
</tr>
<tr>
<td>15.275</td>
<td>2.907</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R21C19[1][B]</td>
<td>picorv32_core/riscv32_alu_u1/n5938_s45/I2</td>
</tr>
<tr>
<td>16.374</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R21C19[1][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n5938_s45/F</td>
</tr>
<tr>
<td>16.380</td>
<td>0.005</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R21C19[0][B]</td>
<td>picorv32_core/riscv32_alu_u1/n5938_s38/I2</td>
</tr>
<tr>
<td>17.479</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R21C19[0][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n5938_s38/F</td>
</tr>
<tr>
<td>18.767</td>
<td>1.289</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R21C21[2][B]</td>
<td>picorv32_core/riscv32_alu_u1/n5938_s36/I1</td>
</tr>
<tr>
<td>19.866</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R21C21[2][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n5938_s36/F</td>
</tr>
<tr>
<td>19.872</td>
<td>0.005</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R21C21[2][A]</td>
<td>picorv32_core/riscv32_alu_u1/n5938_s33/I3</td>
</tr>
<tr>
<td>20.904</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R21C21[2][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n5938_s33/F</td>
</tr>
<tr>
<td>20.904</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R21C21[2][A]</td>
<td style=" font-weight:bold;">picorv32_core/riscv32_alu_u1/reg_wdata_24_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>20.000</td>
<td>20.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>20.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>865</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>21.226</td>
<td>0.244</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C21[2][A]</td>
<td>picorv32_core/riscv32_alu_u1/reg_wdata_24_s0/CLK</td>
</tr>
<tr>
<td>20.826</td>
<td>-0.400</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R21C21[2][A]</td>
<td>picorv32_core/riscv32_alu_u1/reg_wdata_24_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>20.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>10</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.982, 80.100%; route: 0.244, 19.900%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 8.193, 41.635%; route: 11.027, 56.036%; tC2Q: 0.458, 2.329%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.982, 80.100%; route: 0.244, 19.900%</td>
</tr>
</table>
<h3>Path24</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-0.076</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>20.902</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>20.826</td>
</tr>
<tr>
<td class="label">From</td>
<td>picorv32_core/riscv32_alu_u1/op1num_0_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>picorv32_core/riscv32_alu_u1/reg_wdata_17_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>865</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.226</td>
<td>0.244</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R25C17[1][B]</td>
<td>picorv32_core/riscv32_alu_u1/op1num_0_s0/CLK</td>
</tr>
<tr>
<td>1.684</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>11</td>
<td>R25C17[1][B]</td>
<td style=" font-weight:bold;">picorv32_core/riscv32_alu_u1/op1num_0_s0/Q</td>
</tr>
<tr>
<td>4.942</td>
<td>3.258</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R16C40[0][A]</td>
<td>picorv32_core/riscv32_alu_u1/op1_add_op2_res_0_s/I0</td>
</tr>
<tr>
<td>5.645</td>
<td>0.703</td>
<td>tINS</td>
<td>FF</td>
<td>22</td>
<td>R16C40[0][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/op1_add_op2_res_0_s/SUM</td>
</tr>
<tr>
<td>9.413</td>
<td>3.768</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R17C14[1][A]</td>
<td>picorv32_core/riscv32_alu_u1/n5982_s38/I1</td>
</tr>
<tr>
<td>10.445</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>10</td>
<td>R17C14[1][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n5982_s38/F</td>
</tr>
<tr>
<td>11.277</td>
<td>0.832</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C12[3][A]</td>
<td>picorv32_core/riscv32_alu_u1/n5924_s50/I3</td>
</tr>
<tr>
<td>11.903</td>
<td>0.626</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>R18C12[3][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n5924_s50/F</td>
</tr>
<tr>
<td>13.366</td>
<td>1.464</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C17[2][B]</td>
<td>picorv32_core/riscv32_alu_u1/n5924_s81/I3</td>
</tr>
<tr>
<td>14.398</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>R18C17[2][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n5924_s81/F</td>
</tr>
<tr>
<td>16.197</td>
<td>1.798</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C31[1][B]</td>
<td>picorv32_core/riscv32_alu_u1/n5926_s34/I0</td>
</tr>
<tr>
<td>17.019</td>
<td>0.822</td>
<td>tINS</td>
<td>FF</td>
<td>13</td>
<td>R18C31[1][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n5926_s34/F</td>
</tr>
<tr>
<td>19.803</td>
<td>2.785</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R8C16[1][B]</td>
<td>picorv32_core/riscv32_alu_u1/n5952_s33/I0</td>
</tr>
<tr>
<td>20.902</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R8C16[1][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n5952_s33/F</td>
</tr>
<tr>
<td>20.902</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R8C16[1][B]</td>
<td style=" font-weight:bold;">picorv32_core/riscv32_alu_u1/reg_wdata_17_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>20.000</td>
<td>20.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>20.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>865</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>21.226</td>
<td>0.244</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R8C16[1][B]</td>
<td>picorv32_core/riscv32_alu_u1/reg_wdata_17_s0/CLK</td>
</tr>
<tr>
<td>20.826</td>
<td>-0.400</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R8C16[1][B]</td>
<td>picorv32_core/riscv32_alu_u1/reg_wdata_17_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>20.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>7</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.982, 80.100%; route: 0.244, 19.900%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 5.314, 27.007%; route: 13.904, 70.664%; tC2Q: 0.458, 2.329%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.982, 80.100%; route: 0.244, 19.900%</td>
</tr>
</table>
<h3>Path25</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.004</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>20.822</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>20.826</td>
</tr>
<tr>
<td class="label">From</td>
<td>picorv32_core/riscv32_alu_u1/op1num_1_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>picorv32_core/riscv32_alu_u1/cpu_state_0_s2</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>865</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.226</td>
<td>0.244</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R14C15[0][A]</td>
<td>picorv32_core/riscv32_alu_u1/op1num_1_s0/CLK</td>
</tr>
<tr>
<td>1.684</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>12</td>
<td>R14C15[0][A]</td>
<td style=" font-weight:bold;">picorv32_core/riscv32_alu_u1/op1num_1_s0/Q</td>
</tr>
<tr>
<td>4.478</td>
<td>2.793</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C31[1][A]</td>
<td>picorv32_core/riscv32_alu_u1/n246_s64/I0</td>
</tr>
<tr>
<td>5.436</td>
<td>0.958</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C31[1][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n246_s64/COUT</td>
</tr>
<tr>
<td>5.436</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C31[1][B]</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s65/CIN</td>
</tr>
<tr>
<td>5.493</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C31[1][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s65/COUT</td>
</tr>
<tr>
<td>5.493</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C31[2][A]</td>
<td>picorv32_core/riscv32_alu_u1/n246_s65/CIN</td>
</tr>
<tr>
<td>5.550</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C31[2][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n246_s65/COUT</td>
</tr>
<tr>
<td>5.550</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C31[2][B]</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s66/CIN</td>
</tr>
<tr>
<td>5.607</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C31[2][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s66/COUT</td>
</tr>
<tr>
<td>5.607</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C32[0][A]</td>
<td>picorv32_core/riscv32_alu_u1/n246_s66/CIN</td>
</tr>
<tr>
<td>5.664</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C32[0][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n246_s66/COUT</td>
</tr>
<tr>
<td>5.664</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C32[0][B]</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s67/CIN</td>
</tr>
<tr>
<td>5.721</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C32[0][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s67/COUT</td>
</tr>
<tr>
<td>5.721</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C32[1][A]</td>
<td>picorv32_core/riscv32_alu_u1/n246_s67/CIN</td>
</tr>
<tr>
<td>5.778</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C32[1][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n246_s67/COUT</td>
</tr>
<tr>
<td>5.778</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C32[1][B]</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s68/CIN</td>
</tr>
<tr>
<td>5.835</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C32[1][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s68/COUT</td>
</tr>
<tr>
<td>5.835</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C32[2][A]</td>
<td>picorv32_core/riscv32_alu_u1/n246_s68/CIN</td>
</tr>
<tr>
<td>5.892</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C32[2][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n246_s68/COUT</td>
</tr>
<tr>
<td>5.892</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C32[2][B]</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s69/CIN</td>
</tr>
<tr>
<td>5.949</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C32[2][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s69/COUT</td>
</tr>
<tr>
<td>5.949</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C33[0][A]</td>
<td>picorv32_core/riscv32_alu_u1/n246_s69/CIN</td>
</tr>
<tr>
<td>6.006</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C33[0][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n246_s69/COUT</td>
</tr>
<tr>
<td>6.006</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C33[0][B]</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s70/CIN</td>
</tr>
<tr>
<td>6.063</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C33[0][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s70/COUT</td>
</tr>
<tr>
<td>6.063</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C33[1][A]</td>
<td>picorv32_core/riscv32_alu_u1/n246_s70/CIN</td>
</tr>
<tr>
<td>6.120</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C33[1][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n246_s70/COUT</td>
</tr>
<tr>
<td>6.120</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C33[1][B]</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s71/CIN</td>
</tr>
<tr>
<td>6.177</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C33[1][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s71/COUT</td>
</tr>
<tr>
<td>6.177</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C33[2][A]</td>
<td>picorv32_core/riscv32_alu_u1/n246_s71/CIN</td>
</tr>
<tr>
<td>6.234</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C33[2][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n246_s71/COUT</td>
</tr>
<tr>
<td>6.234</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C33[2][B]</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s72/CIN</td>
</tr>
<tr>
<td>6.291</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C33[2][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s72/COUT</td>
</tr>
<tr>
<td>6.291</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C34[0][A]</td>
<td>picorv32_core/riscv32_alu_u1/n246_s72/CIN</td>
</tr>
<tr>
<td>6.348</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C34[0][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n246_s72/COUT</td>
</tr>
<tr>
<td>6.348</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C34[0][B]</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s73/CIN</td>
</tr>
<tr>
<td>6.405</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C34[0][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s73/COUT</td>
</tr>
<tr>
<td>6.405</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C34[1][A]</td>
<td>picorv32_core/riscv32_alu_u1/n246_s73/CIN</td>
</tr>
<tr>
<td>6.462</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C34[1][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n246_s73/COUT</td>
</tr>
<tr>
<td>6.462</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C34[1][B]</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s74/CIN</td>
</tr>
<tr>
<td>6.519</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C34[1][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s74/COUT</td>
</tr>
<tr>
<td>6.519</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C34[2][A]</td>
<td>picorv32_core/riscv32_alu_u1/n246_s74/CIN</td>
</tr>
<tr>
<td>6.576</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C34[2][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n246_s74/COUT</td>
</tr>
<tr>
<td>6.576</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C34[2][B]</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s75/CIN</td>
</tr>
<tr>
<td>6.633</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C34[2][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s75/COUT</td>
</tr>
<tr>
<td>6.633</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C35[0][A]</td>
<td>picorv32_core/riscv32_alu_u1/n246_s75/CIN</td>
</tr>
<tr>
<td>6.690</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C35[0][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n246_s75/COUT</td>
</tr>
<tr>
<td>6.690</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C35[0][B]</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s76/CIN</td>
</tr>
<tr>
<td>6.747</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C35[0][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s76/COUT</td>
</tr>
<tr>
<td>6.747</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C35[1][A]</td>
<td>picorv32_core/riscv32_alu_u1/n246_s76/CIN</td>
</tr>
<tr>
<td>6.804</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C35[1][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n246_s76/COUT</td>
</tr>
<tr>
<td>6.804</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C35[1][B]</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s77/CIN</td>
</tr>
<tr>
<td>6.861</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C35[1][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s77/COUT</td>
</tr>
<tr>
<td>6.861</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C35[2][A]</td>
<td>picorv32_core/riscv32_alu_u1/n246_s77/CIN</td>
</tr>
<tr>
<td>6.918</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C35[2][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n246_s77/COUT</td>
</tr>
<tr>
<td>6.918</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C35[2][B]</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s78/CIN</td>
</tr>
<tr>
<td>6.975</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C35[2][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s78/COUT</td>
</tr>
<tr>
<td>6.975</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R24C36[0][A]</td>
<td>picorv32_core/riscv32_alu_u1/n246_s78/CIN</td>
</tr>
<tr>
<td>7.032</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C36[0][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n246_s78/COUT</td>
</tr>
<tr>
<td>8.569</td>
<td>1.538</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R22C34[3][B]</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s80/I2</td>
</tr>
<tr>
<td>9.601</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>R22C34[3][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/op1_ge_op2_signed_s80/F</td>
</tr>
<tr>
<td>10.416</td>
<td>0.814</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R21C32[3][B]</td>
<td>picorv32_core/riscv32_alu_u1/op1_ge_op2_unsigned_s1/I2</td>
</tr>
<tr>
<td>11.515</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>R21C32[3][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/op1_ge_op2_unsigned_s1/F</td>
</tr>
<tr>
<td>11.526</td>
<td>0.011</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R21C32[0][A]</td>
<td>picorv32_core/riscv32_alu_u1/n1674_s8/I3</td>
</tr>
<tr>
<td>12.552</td>
<td>1.026</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R21C32[0][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n1674_s8/F</td>
</tr>
<tr>
<td>12.970</td>
<td>0.419</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C33[0][A]</td>
<td>picorv32_core/riscv32_alu_u1/n6958_s20/I0</td>
</tr>
<tr>
<td>13.596</td>
<td>0.626</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R21C33[0][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n6958_s20/F</td>
</tr>
<tr>
<td>13.602</td>
<td>0.005</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R21C33[1][A]</td>
<td>picorv32_core/riscv32_alu_u1/n6958_s17/I0</td>
</tr>
<tr>
<td>14.228</td>
<td>0.626</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>R21C33[1][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n6958_s17/F</td>
</tr>
<tr>
<td>14.722</td>
<td>0.495</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R21C34[3][B]</td>
<td>picorv32_core/riscv32_alu_u1/n6959_s15/I0</td>
</tr>
<tr>
<td>15.347</td>
<td>0.625</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R21C34[3][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n6959_s15/F</td>
</tr>
<tr>
<td>15.766</td>
<td>0.419</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C34[1][A]</td>
<td>picorv32_core/riscv32_alu_u1/n6959_s12/I2</td>
</tr>
<tr>
<td>16.392</td>
<td>0.626</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R20C34[1][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n6959_s12/F</td>
</tr>
<tr>
<td>19.790</td>
<td>3.397</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C34[1][A]</td>
<td>picorv32_core/riscv32_alu_u1/n6959_s10/I2</td>
</tr>
<tr>
<td>20.822</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R18C34[1][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n6959_s10/F</td>
</tr>
<tr>
<td>20.822</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C34[1][A]</td>
<td style=" font-weight:bold;">picorv32_core/riscv32_alu_u1/cpu_state_0_s2/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>20.000</td>
<td>20.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>20.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>865</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>21.226</td>
<td>0.244</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C34[1][A]</td>
<td>picorv32_core/riscv32_alu_u1/cpu_state_0_s2/CLK</td>
</tr>
<tr>
<td>20.826</td>
<td>-0.400</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R18C34[1][A]</td>
<td>picorv32_core/riscv32_alu_u1/cpu_state_0_s2</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>20.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>14</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.982, 80.100%; route: 0.244, 19.900%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 9.246, 47.183%; route: 9.892, 50.478%; tC2Q: 0.458, 2.339%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.982, 80.100%; route: 0.244, 19.900%</td>
</tr>
</table>
<h3><a name="Hold_Analysis">Hold Analysis Report</a></h3>
<h4>Report Command:report_timing -hold -max_paths 25 -max_common_paths 1</h4>
<h3>Path1</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.708</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.737</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.029</td>
</tr>
<tr>
<td class="label">From</td>
<td>uart_memory_u1/uart_wdata_2_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>uart_memory_u1/uart_wdata_2_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>865</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.029</td>
<td>0.185</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R23C9[0][A]</td>
<td>uart_memory_u1/uart_wdata_2_s1/CLK</td>
</tr>
<tr>
<td>1.362</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>2</td>
<td>R23C9[0][A]</td>
<td style=" font-weight:bold;">uart_memory_u1/uart_wdata_2_s1/Q</td>
</tr>
<tr>
<td>1.365</td>
<td>0.002</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R23C9[0][A]</td>
<td>uart_memory_u1/n835_s6/I1</td>
</tr>
<tr>
<td>1.737</td>
<td>0.372</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R23C9[0][A]</td>
<td style=" background: #97FFFF;">uart_memory_u1/n835_s6/F</td>
</tr>
<tr>
<td>1.737</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R23C9[0][A]</td>
<td style=" font-weight:bold;">uart_memory_u1/uart_wdata_2_s1/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>865</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.029</td>
<td>0.185</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R23C9[0][A]</td>
<td>uart_memory_u1/uart_wdata_2_s1/CLK</td>
</tr>
<tr>
<td>1.029</td>
<td>0.000</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R23C9[0][A]</td>
<td>uart_memory_u1/uart_wdata_2_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.844, 82.061%; route: 0.185, 17.939%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.844, 82.061%; route: 0.185, 17.939%</td>
</tr>
</table>
<h3>Path2</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.708</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.737</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.029</td>
</tr>
<tr>
<td class="label">From</td>
<td>uart_memory_u1/uart_delay_cnt_3_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>uart_memory_u1/uart_delay_cnt_3_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>865</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.029</td>
<td>0.185</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R16C7[0][A]</td>
<td>uart_memory_u1/uart_delay_cnt_3_s0/CLK</td>
</tr>
<tr>
<td>1.362</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>2</td>
<td>R16C7[0][A]</td>
<td style=" font-weight:bold;">uart_memory_u1/uart_delay_cnt_3_s0/Q</td>
</tr>
<tr>
<td>1.365</td>
<td>0.002</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R16C7[0][A]</td>
<td>uart_memory_u1/n53_s3/I1</td>
</tr>
<tr>
<td>1.737</td>
<td>0.372</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R16C7[0][A]</td>
<td style=" background: #97FFFF;">uart_memory_u1/n53_s3/F</td>
</tr>
<tr>
<td>1.737</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R16C7[0][A]</td>
<td style=" font-weight:bold;">uart_memory_u1/uart_delay_cnt_3_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>865</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.029</td>
<td>0.185</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R16C7[0][A]</td>
<td>uart_memory_u1/uart_delay_cnt_3_s0/CLK</td>
</tr>
<tr>
<td>1.029</td>
<td>0.000</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R16C7[0][A]</td>
<td>uart_memory_u1/uart_delay_cnt_3_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.844, 82.061%; route: 0.185, 17.939%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.844, 82.061%; route: 0.185, 17.939%</td>
</tr>
</table>
<h3>Path3</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.708</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.737</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.029</td>
</tr>
<tr>
<td class="label">From</td>
<td>uart_memory_u1/uart_delay_cnt_14_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>uart_memory_u1/uart_delay_cnt_14_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>865</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.029</td>
<td>0.185</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C5[1][A]</td>
<td>uart_memory_u1/uart_delay_cnt_14_s0/CLK</td>
</tr>
<tr>
<td>1.362</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>3</td>
<td>R17C5[1][A]</td>
<td style=" font-weight:bold;">uart_memory_u1/uart_delay_cnt_14_s0/Q</td>
</tr>
<tr>
<td>1.365</td>
<td>0.002</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C5[1][A]</td>
<td>uart_memory_u1/n42_s3/I0</td>
</tr>
<tr>
<td>1.737</td>
<td>0.372</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R17C5[1][A]</td>
<td style=" background: #97FFFF;">uart_memory_u1/n42_s3/F</td>
</tr>
<tr>
<td>1.737</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R17C5[1][A]</td>
<td style=" font-weight:bold;">uart_memory_u1/uart_delay_cnt_14_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>865</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.029</td>
<td>0.185</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C5[1][A]</td>
<td>uart_memory_u1/uart_delay_cnt_14_s0/CLK</td>
</tr>
<tr>
<td>1.029</td>
<td>0.000</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R17C5[1][A]</td>
<td>uart_memory_u1/uart_delay_cnt_14_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.844, 82.061%; route: 0.185, 17.939%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.844, 82.061%; route: 0.185, 17.939%</td>
</tr>
</table>
<h3>Path4</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.708</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.737</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.029</td>
</tr>
<tr>
<td class="label">From</td>
<td>picorv32_core/riscv32_alu_u1/cpu_state_0_s2</td>
</tr>
<tr>
<td class="label">To</td>
<td>picorv32_core/riscv32_alu_u1/cpu_state_0_s2</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>865</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.029</td>
<td>0.185</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C34[1][A]</td>
<td>picorv32_core/riscv32_alu_u1/cpu_state_0_s2/CLK</td>
</tr>
<tr>
<td>1.362</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>92</td>
<td>R18C34[1][A]</td>
<td style=" font-weight:bold;">picorv32_core/riscv32_alu_u1/cpu_state_0_s2/Q</td>
</tr>
<tr>
<td>1.365</td>
<td>0.002</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C34[1][A]</td>
<td>picorv32_core/riscv32_alu_u1/n6959_s10/I0</td>
</tr>
<tr>
<td>1.737</td>
<td>0.372</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R18C34[1][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n6959_s10/F</td>
</tr>
<tr>
<td>1.737</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C34[1][A]</td>
<td style=" font-weight:bold;">picorv32_core/riscv32_alu_u1/cpu_state_0_s2/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>865</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.029</td>
<td>0.185</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C34[1][A]</td>
<td>picorv32_core/riscv32_alu_u1/cpu_state_0_s2/CLK</td>
</tr>
<tr>
<td>1.029</td>
<td>0.000</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R18C34[1][A]</td>
<td>picorv32_core/riscv32_alu_u1/cpu_state_0_s2</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.844, 82.061%; route: 0.185, 17.939%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.844, 82.061%; route: 0.185, 17.939%</td>
</tr>
</table>
<h3>Path5</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.708</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.737</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.029</td>
</tr>
<tr>
<td class="label">From</td>
<td>picorv32_core/riscv32_alu_u1/mret_reg_27_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>picorv32_core/riscv32_alu_u1/mret_reg_27_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>865</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.029</td>
<td>0.185</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R6C39[1][A]</td>
<td>picorv32_core/riscv32_alu_u1/mret_reg_27_s0/CLK</td>
</tr>
<tr>
<td>1.362</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>3</td>
<td>R6C39[1][A]</td>
<td style=" font-weight:bold;">picorv32_core/riscv32_alu_u1/mret_reg_27_s0/Q</td>
</tr>
<tr>
<td>1.365</td>
<td>0.002</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R6C39[1][A]</td>
<td>picorv32_core/riscv32_alu_u1/n6770_s12/I1</td>
</tr>
<tr>
<td>1.737</td>
<td>0.372</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R6C39[1][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n6770_s12/F</td>
</tr>
<tr>
<td>1.737</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R6C39[1][A]</td>
<td style=" font-weight:bold;">picorv32_core/riscv32_alu_u1/mret_reg_27_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>865</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.029</td>
<td>0.185</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R6C39[1][A]</td>
<td>picorv32_core/riscv32_alu_u1/mret_reg_27_s0/CLK</td>
</tr>
<tr>
<td>1.029</td>
<td>0.000</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R6C39[1][A]</td>
<td>picorv32_core/riscv32_alu_u1/mret_reg_27_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.844, 82.061%; route: 0.185, 17.939%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.844, 82.061%; route: 0.185, 17.939%</td>
</tr>
</table>
<h3>Path6</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.708</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.737</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.029</td>
</tr>
<tr>
<td class="label">From</td>
<td>picorv32_core/riscv32_alu_u1/mem_wstrb_0_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>picorv32_core/riscv32_alu_u1/mem_wstrb_0_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>865</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.029</td>
<td>0.185</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C32[0][A]</td>
<td>picorv32_core/riscv32_alu_u1/mem_wstrb_0_s0/CLK</td>
</tr>
<tr>
<td>1.362</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>6</td>
<td>R20C32[0][A]</td>
<td style=" font-weight:bold;">picorv32_core/riscv32_alu_u1/mem_wstrb_0_s0/Q</td>
</tr>
<tr>
<td>1.365</td>
<td>0.002</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C32[0][A]</td>
<td>picorv32_core/riscv32_alu_u1/n6368_s1/I1</td>
</tr>
<tr>
<td>1.737</td>
<td>0.372</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R20C32[0][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n6368_s1/F</td>
</tr>
<tr>
<td>1.737</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R20C32[0][A]</td>
<td style=" font-weight:bold;">picorv32_core/riscv32_alu_u1/mem_wstrb_0_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>865</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.029</td>
<td>0.185</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C32[0][A]</td>
<td>picorv32_core/riscv32_alu_u1/mem_wstrb_0_s0/CLK</td>
</tr>
<tr>
<td>1.029</td>
<td>0.000</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R20C32[0][A]</td>
<td>picorv32_core/riscv32_alu_u1/mem_wstrb_0_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.844, 82.061%; route: 0.185, 17.939%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.844, 82.061%; route: 0.185, 17.939%</td>
</tr>
</table>
<h3>Path7</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.708</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.737</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.029</td>
</tr>
<tr>
<td class="label">From</td>
<td>picorv32_core/riscv32_alu_u1/mem_wstrb_1_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>picorv32_core/riscv32_alu_u1/mem_wstrb_1_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>865</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.029</td>
<td>0.185</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R14C28[0][A]</td>
<td>picorv32_core/riscv32_alu_u1/mem_wstrb_1_s0/CLK</td>
</tr>
<tr>
<td>1.362</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>6</td>
<td>R14C28[0][A]</td>
<td style=" font-weight:bold;">picorv32_core/riscv32_alu_u1/mem_wstrb_1_s0/Q</td>
</tr>
<tr>
<td>1.365</td>
<td>0.002</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R14C28[0][A]</td>
<td>picorv32_core/riscv32_alu_u1/n6367_s1/I0</td>
</tr>
<tr>
<td>1.737</td>
<td>0.372</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R14C28[0][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n6367_s1/F</td>
</tr>
<tr>
<td>1.737</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R14C28[0][A]</td>
<td style=" font-weight:bold;">picorv32_core/riscv32_alu_u1/mem_wstrb_1_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>865</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.029</td>
<td>0.185</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R14C28[0][A]</td>
<td>picorv32_core/riscv32_alu_u1/mem_wstrb_1_s0/CLK</td>
</tr>
<tr>
<td>1.029</td>
<td>0.000</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R14C28[0][A]</td>
<td>picorv32_core/riscv32_alu_u1/mem_wstrb_1_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.844, 82.061%; route: 0.185, 17.939%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.844, 82.061%; route: 0.185, 17.939%</td>
</tr>
</table>
<h3>Path8</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.708</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.737</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.029</td>
</tr>
<tr>
<td class="label">From</td>
<td>picorv32_core/uart_debug_u1/u_uart_txd/state_0_s3</td>
</tr>
<tr>
<td class="label">To</td>
<td>picorv32_core/uart_debug_u1/u_uart_txd/state_0_s3</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>865</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.029</td>
<td>0.185</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C6[1][A]</td>
<td>picorv32_core/uart_debug_u1/u_uart_txd/state_0_s3/CLK</td>
</tr>
<tr>
<td>1.362</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>6</td>
<td>R11C6[1][A]</td>
<td style=" font-weight:bold;">picorv32_core/uart_debug_u1/u_uart_txd/state_0_s3/Q</td>
</tr>
<tr>
<td>1.365</td>
<td>0.002</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C6[1][A]</td>
<td>picorv32_core/uart_debug_u1/u_uart_txd/n108_s3/I0</td>
</tr>
<tr>
<td>1.737</td>
<td>0.372</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R11C6[1][A]</td>
<td style=" background: #97FFFF;">picorv32_core/uart_debug_u1/u_uart_txd/n108_s3/F</td>
</tr>
<tr>
<td>1.737</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R11C6[1][A]</td>
<td style=" font-weight:bold;">picorv32_core/uart_debug_u1/u_uart_txd/state_0_s3/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>865</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.029</td>
<td>0.185</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C6[1][A]</td>
<td>picorv32_core/uart_debug_u1/u_uart_txd/state_0_s3/CLK</td>
</tr>
<tr>
<td>1.029</td>
<td>0.000</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R11C6[1][A]</td>
<td>picorv32_core/uart_debug_u1/u_uart_txd/state_0_s3</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.844, 82.061%; route: 0.185, 17.939%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.844, 82.061%; route: 0.185, 17.939%</td>
</tr>
</table>
<h3>Path9</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.708</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.737</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.029</td>
</tr>
<tr>
<td class="label">From</td>
<td>picorv32_core/uart_debug_u1/reset_out_s10</td>
</tr>
<tr>
<td class="label">To</td>
<td>picorv32_core/uart_debug_u1/reset_out_s10</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>865</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.029</td>
<td>0.185</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R12C10[0][A]</td>
<td>picorv32_core/uart_debug_u1/reset_out_s10/CLK</td>
</tr>
<tr>
<td>1.362</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>248</td>
<td>R12C10[0][A]</td>
<td style=" font-weight:bold;">picorv32_core/uart_debug_u1/reset_out_s10/Q</td>
</tr>
<tr>
<td>1.365</td>
<td>0.002</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R12C10[0][A]</td>
<td>picorv32_core/uart_debug_u1/n81_s8/I0</td>
</tr>
<tr>
<td>1.737</td>
<td>0.372</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R12C10[0][A]</td>
<td style=" background: #97FFFF;">picorv32_core/uart_debug_u1/n81_s8/F</td>
</tr>
<tr>
<td>1.737</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R12C10[0][A]</td>
<td style=" font-weight:bold;">picorv32_core/uart_debug_u1/reset_out_s10/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>865</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.029</td>
<td>0.185</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R12C10[0][A]</td>
<td>picorv32_core/uart_debug_u1/reset_out_s10/CLK</td>
</tr>
<tr>
<td>1.029</td>
<td>0.000</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R12C10[0][A]</td>
<td>picorv32_core/uart_debug_u1/reset_out_s10</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.844, 82.061%; route: 0.185, 17.939%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.844, 82.061%; route: 0.185, 17.939%</td>
</tr>
</table>
<h3>Path10</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.708</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.737</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.029</td>
</tr>
<tr>
<td class="label">From</td>
<td>picorv32_core/uart_debug_u1/uart_cnt_2_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>picorv32_core/uart_debug_u1/uart_cnt_2_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>865</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.029</td>
<td>0.185</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R12C10[1][A]</td>
<td>picorv32_core/uart_debug_u1/uart_cnt_2_s0/CLK</td>
</tr>
<tr>
<td>1.362</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>3</td>
<td>R12C10[1][A]</td>
<td style=" font-weight:bold;">picorv32_core/uart_debug_u1/uart_cnt_2_s0/Q</td>
</tr>
<tr>
<td>1.365</td>
<td>0.002</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R12C10[1][A]</td>
<td>picorv32_core/uart_debug_u1/n61_s1/I2</td>
</tr>
<tr>
<td>1.737</td>
<td>0.372</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R12C10[1][A]</td>
<td style=" background: #97FFFF;">picorv32_core/uart_debug_u1/n61_s1/F</td>
</tr>
<tr>
<td>1.737</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R12C10[1][A]</td>
<td style=" font-weight:bold;">picorv32_core/uart_debug_u1/uart_cnt_2_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>865</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.029</td>
<td>0.185</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R12C10[1][A]</td>
<td>picorv32_core/uart_debug_u1/uart_cnt_2_s0/CLK</td>
</tr>
<tr>
<td>1.029</td>
<td>0.000</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R12C10[1][A]</td>
<td>picorv32_core/uart_debug_u1/uart_cnt_2_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.844, 82.061%; route: 0.185, 17.939%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.844, 82.061%; route: 0.185, 17.939%</td>
</tr>
</table>
<h3>Path11</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.709</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.738</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.029</td>
</tr>
<tr>
<td class="label">From</td>
<td>uart_memory_u1/u_uart_txd/cnt_clk_4_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>uart_memory_u1/u_uart_txd/cnt_clk_4_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>865</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.029</td>
<td>0.185</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R24C6[0][A]</td>
<td>uart_memory_u1/u_uart_txd/cnt_clk_4_s0/CLK</td>
</tr>
<tr>
<td>1.362</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>3</td>
<td>R24C6[0][A]</td>
<td style=" font-weight:bold;">uart_memory_u1/u_uart_txd/cnt_clk_4_s0/Q</td>
</tr>
<tr>
<td>1.366</td>
<td>0.004</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R24C6[0][A]</td>
<td>uart_memory_u1/u_uart_txd/n118_s3/I3</td>
</tr>
<tr>
<td>1.738</td>
<td>0.372</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R24C6[0][A]</td>
<td style=" background: #97FFFF;">uart_memory_u1/u_uart_txd/n118_s3/F</td>
</tr>
<tr>
<td>1.738</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R24C6[0][A]</td>
<td style=" font-weight:bold;">uart_memory_u1/u_uart_txd/cnt_clk_4_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>865</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.029</td>
<td>0.185</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R24C6[0][A]</td>
<td>uart_memory_u1/u_uart_txd/cnt_clk_4_s0/CLK</td>
</tr>
<tr>
<td>1.029</td>
<td>0.000</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R24C6[0][A]</td>
<td>uart_memory_u1/u_uart_txd/cnt_clk_4_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.844, 82.061%; route: 0.185, 17.939%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.372, 52.478%; route: 0.004, 0.500%; tC2Q: 0.333, 47.023%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.844, 82.061%; route: 0.185, 17.939%</td>
</tr>
</table>
<h3>Path12</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.709</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.738</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.029</td>
</tr>
<tr>
<td class="label">From</td>
<td>uart_memory_u1/u_uart_recv/state_0_s3</td>
</tr>
<tr>
<td class="label">To</td>
<td>uart_memory_u1/u_uart_recv/state_0_s3</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>865</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.029</td>
<td>0.185</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R22C8[0][A]</td>
<td>uart_memory_u1/u_uart_recv/state_0_s3/CLK</td>
</tr>
<tr>
<td>1.362</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>6</td>
<td>R22C8[0][A]</td>
<td style=" font-weight:bold;">uart_memory_u1/u_uart_recv/state_0_s3/Q</td>
</tr>
<tr>
<td>1.366</td>
<td>0.004</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R22C8[0][A]</td>
<td>uart_memory_u1/u_uart_recv/n70_s3/I0</td>
</tr>
<tr>
<td>1.738</td>
<td>0.372</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R22C8[0][A]</td>
<td style=" background: #97FFFF;">uart_memory_u1/u_uart_recv/n70_s3/F</td>
</tr>
<tr>
<td>1.738</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R22C8[0][A]</td>
<td style=" font-weight:bold;">uart_memory_u1/u_uart_recv/state_0_s3/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>865</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.029</td>
<td>0.185</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R22C8[0][A]</td>
<td>uart_memory_u1/u_uart_recv/state_0_s3/CLK</td>
</tr>
<tr>
<td>1.029</td>
<td>0.000</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R22C8[0][A]</td>
<td>uart_memory_u1/u_uart_recv/state_0_s3</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.844, 82.061%; route: 0.185, 17.939%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.372, 52.478%; route: 0.004, 0.500%; tC2Q: 0.333, 47.023%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.844, 82.061%; route: 0.185, 17.939%</td>
</tr>
</table>
<h3>Path13</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.709</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.738</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.029</td>
</tr>
<tr>
<td class="label">From</td>
<td>uart_memory_u1/u_uart_recv/state_2_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>uart_memory_u1/u_uart_recv/state_2_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>865</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.029</td>
<td>0.185</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R22C8[1][A]</td>
<td>uart_memory_u1/u_uart_recv/state_2_s1/CLK</td>
</tr>
<tr>
<td>1.362</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>4</td>
<td>R22C8[1][A]</td>
<td style=" font-weight:bold;">uart_memory_u1/u_uart_recv/state_2_s1/Q</td>
</tr>
<tr>
<td>1.366</td>
<td>0.004</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R22C8[1][A]</td>
<td>uart_memory_u1/u_uart_recv/n68_s1/I2</td>
</tr>
<tr>
<td>1.738</td>
<td>0.372</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R22C8[1][A]</td>
<td style=" background: #97FFFF;">uart_memory_u1/u_uart_recv/n68_s1/F</td>
</tr>
<tr>
<td>1.738</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R22C8[1][A]</td>
<td style=" font-weight:bold;">uart_memory_u1/u_uart_recv/state_2_s1/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>865</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.029</td>
<td>0.185</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R22C8[1][A]</td>
<td>uart_memory_u1/u_uart_recv/state_2_s1/CLK</td>
</tr>
<tr>
<td>1.029</td>
<td>0.000</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R22C8[1][A]</td>
<td>uart_memory_u1/u_uart_recv/state_2_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.844, 82.061%; route: 0.185, 17.939%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.372, 52.478%; route: 0.004, 0.500%; tC2Q: 0.333, 47.023%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.844, 82.061%; route: 0.185, 17.939%</td>
</tr>
</table>
<h3>Path14</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.709</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.738</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.029</td>
</tr>
<tr>
<td class="label">From</td>
<td>uart_memory_u1/u_uart_recv/cnt_clk_0_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>uart_memory_u1/u_uart_recv/cnt_clk_0_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>865</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.029</td>
<td>0.185</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R24C11[0][A]</td>
<td>uart_memory_u1/u_uart_recv/cnt_clk_0_s0/CLK</td>
</tr>
<tr>
<td>1.362</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>5</td>
<td>R24C11[0][A]</td>
<td style=" font-weight:bold;">uart_memory_u1/u_uart_recv/cnt_clk_0_s0/Q</td>
</tr>
<tr>
<td>1.366</td>
<td>0.004</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R24C11[0][A]</td>
<td>uart_memory_u1/u_uart_recv/n86_s3/I2</td>
</tr>
<tr>
<td>1.738</td>
<td>0.372</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R24C11[0][A]</td>
<td style=" background: #97FFFF;">uart_memory_u1/u_uart_recv/n86_s3/F</td>
</tr>
<tr>
<td>1.738</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R24C11[0][A]</td>
<td style=" font-weight:bold;">uart_memory_u1/u_uart_recv/cnt_clk_0_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>865</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.029</td>
<td>0.185</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R24C11[0][A]</td>
<td>uart_memory_u1/u_uart_recv/cnt_clk_0_s0/CLK</td>
</tr>
<tr>
<td>1.029</td>
<td>0.000</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R24C11[0][A]</td>
<td>uart_memory_u1/u_uart_recv/cnt_clk_0_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.844, 82.061%; route: 0.185, 17.939%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.372, 52.478%; route: 0.004, 0.500%; tC2Q: 0.333, 47.023%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.844, 82.061%; route: 0.185, 17.939%</td>
</tr>
</table>
<h3>Path15</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.709</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.738</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.029</td>
</tr>
<tr>
<td class="label">From</td>
<td>uart_memory_u1/u_uart_recv/cnt_clk_1_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>uart_memory_u1/u_uart_recv/cnt_clk_1_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>865</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.029</td>
<td>0.185</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C10[0][A]</td>
<td>uart_memory_u1/u_uart_recv/cnt_clk_1_s0/CLK</td>
</tr>
<tr>
<td>1.362</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>5</td>
<td>R18C10[0][A]</td>
<td style=" font-weight:bold;">uart_memory_u1/u_uart_recv/cnt_clk_1_s0/Q</td>
</tr>
<tr>
<td>1.366</td>
<td>0.004</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C10[0][A]</td>
<td>uart_memory_u1/u_uart_recv/n85_s2/I3</td>
</tr>
<tr>
<td>1.738</td>
<td>0.372</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R18C10[0][A]</td>
<td style=" background: #97FFFF;">uart_memory_u1/u_uart_recv/n85_s2/F</td>
</tr>
<tr>
<td>1.738</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C10[0][A]</td>
<td style=" font-weight:bold;">uart_memory_u1/u_uart_recv/cnt_clk_1_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>865</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.029</td>
<td>0.185</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C10[0][A]</td>
<td>uart_memory_u1/u_uart_recv/cnt_clk_1_s0/CLK</td>
</tr>
<tr>
<td>1.029</td>
<td>0.000</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R18C10[0][A]</td>
<td>uart_memory_u1/u_uart_recv/cnt_clk_1_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.844, 82.061%; route: 0.185, 17.939%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.372, 52.478%; route: 0.004, 0.500%; tC2Q: 0.333, 47.023%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.844, 82.061%; route: 0.185, 17.939%</td>
</tr>
</table>
<h3>Path16</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.709</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.738</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.029</td>
</tr>
<tr>
<td class="label">From</td>
<td>uart_memory_u1/u_uart_recv/cnt_clk_4_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>uart_memory_u1/u_uart_recv/cnt_clk_4_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>865</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.029</td>
<td>0.185</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C9[0][A]</td>
<td>uart_memory_u1/u_uart_recv/cnt_clk_4_s0/CLK</td>
</tr>
<tr>
<td>1.362</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>3</td>
<td>R18C9[0][A]</td>
<td style=" font-weight:bold;">uart_memory_u1/u_uart_recv/cnt_clk_4_s0/Q</td>
</tr>
<tr>
<td>1.366</td>
<td>0.004</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C9[0][A]</td>
<td>uart_memory_u1/u_uart_recv/n82_s1/I2</td>
</tr>
<tr>
<td>1.738</td>
<td>0.372</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R18C9[0][A]</td>
<td style=" background: #97FFFF;">uart_memory_u1/u_uart_recv/n82_s1/F</td>
</tr>
<tr>
<td>1.738</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C9[0][A]</td>
<td style=" font-weight:bold;">uart_memory_u1/u_uart_recv/cnt_clk_4_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>865</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.029</td>
<td>0.185</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C9[0][A]</td>
<td>uart_memory_u1/u_uart_recv/cnt_clk_4_s0/CLK</td>
</tr>
<tr>
<td>1.029</td>
<td>0.000</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R18C9[0][A]</td>
<td>uart_memory_u1/u_uart_recv/cnt_clk_4_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.844, 82.061%; route: 0.185, 17.939%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.372, 52.478%; route: 0.004, 0.500%; tC2Q: 0.333, 47.023%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.844, 82.061%; route: 0.185, 17.939%</td>
</tr>
</table>
<h3>Path17</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.709</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.738</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.029</td>
</tr>
<tr>
<td class="label">From</td>
<td>uart_memory_u1/uart_delay_cnt_0_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>uart_memory_u1/uart_delay_cnt_0_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>865</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.029</td>
<td>0.185</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R16C7[1][A]</td>
<td>uart_memory_u1/uart_delay_cnt_0_s0/CLK</td>
</tr>
<tr>
<td>1.362</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>5</td>
<td>R16C7[1][A]</td>
<td style=" font-weight:bold;">uart_memory_u1/uart_delay_cnt_0_s0/Q</td>
</tr>
<tr>
<td>1.366</td>
<td>0.004</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R16C7[1][A]</td>
<td>uart_memory_u1/n56_s2/I0</td>
</tr>
<tr>
<td>1.738</td>
<td>0.372</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R16C7[1][A]</td>
<td style=" background: #97FFFF;">uart_memory_u1/n56_s2/F</td>
</tr>
<tr>
<td>1.738</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R16C7[1][A]</td>
<td style=" font-weight:bold;">uart_memory_u1/uart_delay_cnt_0_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>865</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.029</td>
<td>0.185</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R16C7[1][A]</td>
<td>uart_memory_u1/uart_delay_cnt_0_s0/CLK</td>
</tr>
<tr>
<td>1.029</td>
<td>0.000</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R16C7[1][A]</td>
<td>uart_memory_u1/uart_delay_cnt_0_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.844, 82.061%; route: 0.185, 17.939%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.372, 52.478%; route: 0.004, 0.500%; tC2Q: 0.333, 47.023%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.844, 82.061%; route: 0.185, 17.939%</td>
</tr>
</table>
<h3>Path18</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.709</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.738</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.029</td>
</tr>
<tr>
<td class="label">From</td>
<td>uart_memory_u1/uart_delay_cnt_4_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>uart_memory_u1/uart_delay_cnt_4_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>865</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.029</td>
<td>0.185</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C7[0][A]</td>
<td>uart_memory_u1/uart_delay_cnt_4_s0/CLK</td>
</tr>
<tr>
<td>1.362</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>5</td>
<td>R17C7[0][A]</td>
<td style=" font-weight:bold;">uart_memory_u1/uart_delay_cnt_4_s0/Q</td>
</tr>
<tr>
<td>1.366</td>
<td>0.004</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C7[0][A]</td>
<td>uart_memory_u1/n52_s3/I0</td>
</tr>
<tr>
<td>1.738</td>
<td>0.372</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R17C7[0][A]</td>
<td style=" background: #97FFFF;">uart_memory_u1/n52_s3/F</td>
</tr>
<tr>
<td>1.738</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R17C7[0][A]</td>
<td style=" font-weight:bold;">uart_memory_u1/uart_delay_cnt_4_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>865</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.029</td>
<td>0.185</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C7[0][A]</td>
<td>uart_memory_u1/uart_delay_cnt_4_s0/CLK</td>
</tr>
<tr>
<td>1.029</td>
<td>0.000</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R17C7[0][A]</td>
<td>uart_memory_u1/uart_delay_cnt_4_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.844, 82.061%; route: 0.185, 17.939%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.372, 52.478%; route: 0.004, 0.500%; tC2Q: 0.333, 47.023%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.844, 82.061%; route: 0.185, 17.939%</td>
</tr>
</table>
<h3>Path19</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.709</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.738</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.029</td>
</tr>
<tr>
<td class="label">From</td>
<td>uart_memory_u1/uart_delay_cnt_6_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>uart_memory_u1/uart_delay_cnt_6_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>865</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.029</td>
<td>0.185</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C7[0][A]</td>
<td>uart_memory_u1/uart_delay_cnt_6_s0/CLK</td>
</tr>
<tr>
<td>1.362</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>3</td>
<td>R18C7[0][A]</td>
<td style=" font-weight:bold;">uart_memory_u1/uart_delay_cnt_6_s0/Q</td>
</tr>
<tr>
<td>1.366</td>
<td>0.004</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C7[0][A]</td>
<td>uart_memory_u1/n50_s3/I1</td>
</tr>
<tr>
<td>1.738</td>
<td>0.372</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R18C7[0][A]</td>
<td style=" background: #97FFFF;">uart_memory_u1/n50_s3/F</td>
</tr>
<tr>
<td>1.738</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C7[0][A]</td>
<td style=" font-weight:bold;">uart_memory_u1/uart_delay_cnt_6_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>865</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.029</td>
<td>0.185</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C7[0][A]</td>
<td>uart_memory_u1/uart_delay_cnt_6_s0/CLK</td>
</tr>
<tr>
<td>1.029</td>
<td>0.000</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R18C7[0][A]</td>
<td>uart_memory_u1/uart_delay_cnt_6_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.844, 82.061%; route: 0.185, 17.939%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.372, 52.478%; route: 0.004, 0.500%; tC2Q: 0.333, 47.023%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.844, 82.061%; route: 0.185, 17.939%</td>
</tr>
</table>
<h3>Path20</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.709</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.738</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.029</td>
</tr>
<tr>
<td class="label">From</td>
<td>uart_memory_u1/uart_delay_cnt_7_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>uart_memory_u1/uart_delay_cnt_7_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>865</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.029</td>
<td>0.185</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C6[0][A]</td>
<td>uart_memory_u1/uart_delay_cnt_7_s0/CLK</td>
</tr>
<tr>
<td>1.362</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>5</td>
<td>R17C6[0][A]</td>
<td style=" font-weight:bold;">uart_memory_u1/uart_delay_cnt_7_s0/Q</td>
</tr>
<tr>
<td>1.366</td>
<td>0.004</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C6[0][A]</td>
<td>uart_memory_u1/n49_s3/I0</td>
</tr>
<tr>
<td>1.738</td>
<td>0.372</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R17C6[0][A]</td>
<td style=" background: #97FFFF;">uart_memory_u1/n49_s3/F</td>
</tr>
<tr>
<td>1.738</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R17C6[0][A]</td>
<td style=" font-weight:bold;">uart_memory_u1/uart_delay_cnt_7_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>865</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.029</td>
<td>0.185</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C6[0][A]</td>
<td>uart_memory_u1/uart_delay_cnt_7_s0/CLK</td>
</tr>
<tr>
<td>1.029</td>
<td>0.000</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R17C6[0][A]</td>
<td>uart_memory_u1/uart_delay_cnt_7_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.844, 82.061%; route: 0.185, 17.939%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.372, 52.478%; route: 0.004, 0.500%; tC2Q: 0.333, 47.023%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.844, 82.061%; route: 0.185, 17.939%</td>
</tr>
</table>
<h3>Path21</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.709</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.738</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.029</td>
</tr>
<tr>
<td class="label">From</td>
<td>uart_memory_u1/uart_delay_cnt_9_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>uart_memory_u1/uart_delay_cnt_9_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>865</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.029</td>
<td>0.185</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C6[0][A]</td>
<td>uart_memory_u1/uart_delay_cnt_9_s0/CLK</td>
</tr>
<tr>
<td>1.362</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>4</td>
<td>R18C6[0][A]</td>
<td style=" font-weight:bold;">uart_memory_u1/uart_delay_cnt_9_s0/Q</td>
</tr>
<tr>
<td>1.366</td>
<td>0.004</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C6[0][A]</td>
<td>uart_memory_u1/n47_s1/I2</td>
</tr>
<tr>
<td>1.738</td>
<td>0.372</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R18C6[0][A]</td>
<td style=" background: #97FFFF;">uart_memory_u1/n47_s1/F</td>
</tr>
<tr>
<td>1.738</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C6[0][A]</td>
<td style=" font-weight:bold;">uart_memory_u1/uart_delay_cnt_9_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>865</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.029</td>
<td>0.185</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C6[0][A]</td>
<td>uart_memory_u1/uart_delay_cnt_9_s0/CLK</td>
</tr>
<tr>
<td>1.029</td>
<td>0.000</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R18C6[0][A]</td>
<td>uart_memory_u1/uart_delay_cnt_9_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.844, 82.061%; route: 0.185, 17.939%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.372, 52.478%; route: 0.004, 0.500%; tC2Q: 0.333, 47.023%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.844, 82.061%; route: 0.185, 17.939%</td>
</tr>
</table>
<h3>Path22</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.709</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.738</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.029</td>
</tr>
<tr>
<td class="label">From</td>
<td>uart_memory_u1/uart_delay_cnt_10_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>uart_memory_u1/uart_delay_cnt_10_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>865</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.029</td>
<td>0.185</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C6[1][A]</td>
<td>uart_memory_u1/uart_delay_cnt_10_s0/CLK</td>
</tr>
<tr>
<td>1.362</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>3</td>
<td>R18C6[1][A]</td>
<td style=" font-weight:bold;">uart_memory_u1/uart_delay_cnt_10_s0/Q</td>
</tr>
<tr>
<td>1.366</td>
<td>0.004</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C6[1][A]</td>
<td>uart_memory_u1/n46_s4/I1</td>
</tr>
<tr>
<td>1.738</td>
<td>0.372</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R18C6[1][A]</td>
<td style=" background: #97FFFF;">uart_memory_u1/n46_s4/F</td>
</tr>
<tr>
<td>1.738</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C6[1][A]</td>
<td style=" font-weight:bold;">uart_memory_u1/uart_delay_cnt_10_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>865</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.029</td>
<td>0.185</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C6[1][A]</td>
<td>uart_memory_u1/uart_delay_cnt_10_s0/CLK</td>
</tr>
<tr>
<td>1.029</td>
<td>0.000</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R18C6[1][A]</td>
<td>uart_memory_u1/uart_delay_cnt_10_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.844, 82.061%; route: 0.185, 17.939%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.372, 52.478%; route: 0.004, 0.500%; tC2Q: 0.333, 47.023%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.844, 82.061%; route: 0.185, 17.939%</td>
</tr>
</table>
<h3>Path23</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.709</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.738</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.029</td>
</tr>
<tr>
<td class="label">From</td>
<td>uart_memory_u1/uart_delay_cnt_11_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>uart_memory_u1/uart_delay_cnt_11_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>865</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.029</td>
<td>0.185</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C5[0][A]</td>
<td>uart_memory_u1/uart_delay_cnt_11_s0/CLK</td>
</tr>
<tr>
<td>1.362</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>5</td>
<td>R18C5[0][A]</td>
<td style=" font-weight:bold;">uart_memory_u1/uart_delay_cnt_11_s0/Q</td>
</tr>
<tr>
<td>1.366</td>
<td>0.004</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C5[0][A]</td>
<td>uart_memory_u1/n45_s3/I0</td>
</tr>
<tr>
<td>1.738</td>
<td>0.372</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R18C5[0][A]</td>
<td style=" background: #97FFFF;">uart_memory_u1/n45_s3/F</td>
</tr>
<tr>
<td>1.738</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C5[0][A]</td>
<td style=" font-weight:bold;">uart_memory_u1/uart_delay_cnt_11_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>865</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.029</td>
<td>0.185</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C5[0][A]</td>
<td>uart_memory_u1/uart_delay_cnt_11_s0/CLK</td>
</tr>
<tr>
<td>1.029</td>
<td>0.000</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R18C5[0][A]</td>
<td>uart_memory_u1/uart_delay_cnt_11_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.844, 82.061%; route: 0.185, 17.939%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.372, 52.478%; route: 0.004, 0.500%; tC2Q: 0.333, 47.023%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.844, 82.061%; route: 0.185, 17.939%</td>
</tr>
</table>
<h3>Path24</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.709</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.738</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.029</td>
</tr>
<tr>
<td class="label">From</td>
<td>picorv32_core/riscv32_alu_u1/mret_reg_18_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>picorv32_core/riscv32_alu_u1/mret_reg_18_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>865</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.029</td>
<td>0.185</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R8C36[1][A]</td>
<td>picorv32_core/riscv32_alu_u1/mret_reg_18_s0/CLK</td>
</tr>
<tr>
<td>1.362</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>3</td>
<td>R8C36[1][A]</td>
<td style=" font-weight:bold;">picorv32_core/riscv32_alu_u1/mret_reg_18_s0/Q</td>
</tr>
<tr>
<td>1.366</td>
<td>0.004</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R8C36[1][A]</td>
<td>picorv32_core/riscv32_alu_u1/n6788_s12/I1</td>
</tr>
<tr>
<td>1.738</td>
<td>0.372</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R8C36[1][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n6788_s12/F</td>
</tr>
<tr>
<td>1.738</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R8C36[1][A]</td>
<td style=" font-weight:bold;">picorv32_core/riscv32_alu_u1/mret_reg_18_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>865</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.029</td>
<td>0.185</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R8C36[1][A]</td>
<td>picorv32_core/riscv32_alu_u1/mret_reg_18_s0/CLK</td>
</tr>
<tr>
<td>1.029</td>
<td>0.000</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R8C36[1][A]</td>
<td>picorv32_core/riscv32_alu_u1/mret_reg_18_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.844, 82.061%; route: 0.185, 17.939%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.372, 52.478%; route: 0.004, 0.500%; tC2Q: 0.333, 47.023%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.844, 82.061%; route: 0.185, 17.939%</td>
</tr>
</table>
<h3>Path25</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.709</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.738</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.029</td>
</tr>
<tr>
<td class="label">From</td>
<td>picorv32_core/riscv32_alu_u1/mret_reg_20_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>picorv32_core/riscv32_alu_u1/mret_reg_20_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>865</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.029</td>
<td>0.185</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R15C37[1][A]</td>
<td>picorv32_core/riscv32_alu_u1/mret_reg_20_s0/CLK</td>
</tr>
<tr>
<td>1.362</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>3</td>
<td>R15C37[1][A]</td>
<td style=" font-weight:bold;">picorv32_core/riscv32_alu_u1/mret_reg_20_s0/Q</td>
</tr>
<tr>
<td>1.366</td>
<td>0.004</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R15C37[1][A]</td>
<td>picorv32_core/riscv32_alu_u1/n6784_s12/I1</td>
</tr>
<tr>
<td>1.738</td>
<td>0.372</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R15C37[1][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n6784_s12/F</td>
</tr>
<tr>
<td>1.738</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R15C37[1][A]</td>
<td style=" font-weight:bold;">picorv32_core/riscv32_alu_u1/mret_reg_20_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>865</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.029</td>
<td>0.185</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R15C37[1][A]</td>
<td>picorv32_core/riscv32_alu_u1/mret_reg_20_s0/CLK</td>
</tr>
<tr>
<td>1.029</td>
<td>0.000</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R15C37[1][A]</td>
<td>picorv32_core/riscv32_alu_u1/mret_reg_20_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.844, 82.061%; route: 0.185, 17.939%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.372, 52.478%; route: 0.004, 0.500%; tC2Q: 0.333, 47.023%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.844, 82.061%; route: 0.185, 17.939%</td>
</tr>
</table>
<h3><a name="Recovery_Analysis">Recovery Analysis Report</a></h3>
<h4>Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1</h4>
<h3>Path1</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>16.368</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>4.815</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>21.182</td>
</tr>
<tr>
<td class="label">From</td>
<td>picorv32_core/uart_debug_u1/reset_out_s10</td>
</tr>
<tr>
<td class="label">To</td>
<td>uart_memory_u1/u_uart_txd/state_1_s3</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>865</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.226</td>
<td>0.244</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R12C10[0][A]</td>
<td>picorv32_core/uart_debug_u1/reset_out_s10/CLK</td>
</tr>
<tr>
<td>1.684</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>248</td>
<td>R12C10[0][A]</td>
<td style=" font-weight:bold;">picorv32_core/uart_debug_u1/reset_out_s10/Q</td>
</tr>
<tr>
<td>4.815</td>
<td>3.131</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R23C6[0][A]</td>
<td style=" font-weight:bold;">uart_memory_u1/u_uart_txd/state_1_s3/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>20.000</td>
<td>20.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>20.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>865</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>21.226</td>
<td>0.244</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R23C6[0][A]</td>
<td>uart_memory_u1/u_uart_txd/state_1_s3/CLK</td>
</tr>
<tr>
<td>21.182</td>
<td>-0.043</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R23C6[0][A]</td>
<td>uart_memory_u1/u_uart_txd/state_1_s3</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>20.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.982, 80.100%; route: 0.244, 19.900%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 3.131, 87.230%; tC2Q: 0.458, 12.770%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.982, 80.100%; route: 0.244, 19.900%</td>
</tr>
</table>
<h3>Path2</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>16.368</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>4.815</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>21.182</td>
</tr>
<tr>
<td class="label">From</td>
<td>picorv32_core/uart_debug_u1/reset_out_s10</td>
</tr>
<tr>
<td class="label">To</td>
<td>uart_memory_u1/u_uart_txd/state_3_s10</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>865</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.226</td>
<td>0.244</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R12C10[0][A]</td>
<td>picorv32_core/uart_debug_u1/reset_out_s10/CLK</td>
</tr>
<tr>
<td>1.684</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>248</td>
<td>R12C10[0][A]</td>
<td style=" font-weight:bold;">picorv32_core/uart_debug_u1/reset_out_s10/Q</td>
</tr>
<tr>
<td>4.815</td>
<td>3.131</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R24C7[0][A]</td>
<td style=" font-weight:bold;">uart_memory_u1/u_uart_txd/state_3_s10/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>20.000</td>
<td>20.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>20.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>865</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>21.226</td>
<td>0.244</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R24C7[0][A]</td>
<td>uart_memory_u1/u_uart_txd/state_3_s10/CLK</td>
</tr>
<tr>
<td>21.182</td>
<td>-0.043</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R24C7[0][A]</td>
<td>uart_memory_u1/u_uart_txd/state_3_s10</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>20.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.982, 80.100%; route: 0.244, 19.900%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 3.131, 87.230%; tC2Q: 0.458, 12.770%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.982, 80.100%; route: 0.244, 19.900%</td>
</tr>
</table>
<h3>Path3</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>16.368</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>4.815</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>21.182</td>
</tr>
<tr>
<td class="label">From</td>
<td>picorv32_core/uart_debug_u1/reset_out_s10</td>
</tr>
<tr>
<td class="label">To</td>
<td>uart_memory_u1/u_uart_txd/state_0_s3</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>865</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.226</td>
<td>0.244</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R12C10[0][A]</td>
<td>picorv32_core/uart_debug_u1/reset_out_s10/CLK</td>
</tr>
<tr>
<td>1.684</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>248</td>
<td>R12C10[0][A]</td>
<td style=" font-weight:bold;">picorv32_core/uart_debug_u1/reset_out_s10/Q</td>
</tr>
<tr>
<td>4.815</td>
<td>3.131</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R23C5[0][A]</td>
<td style=" font-weight:bold;">uart_memory_u1/u_uart_txd/state_0_s3/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>20.000</td>
<td>20.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>20.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>865</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>21.226</td>
<td>0.244</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R23C5[0][A]</td>
<td>uart_memory_u1/u_uart_txd/state_0_s3/CLK</td>
</tr>
<tr>
<td>21.182</td>
<td>-0.043</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R23C5[0][A]</td>
<td>uart_memory_u1/u_uart_txd/state_0_s3</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>20.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.982, 80.100%; route: 0.244, 19.900%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 3.131, 87.230%; tC2Q: 0.458, 12.770%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.982, 80.100%; route: 0.244, 19.900%</td>
</tr>
</table>
<h3>Path4</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>16.368</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>4.815</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>21.182</td>
</tr>
<tr>
<td class="label">From</td>
<td>picorv32_core/uart_debug_u1/reset_out_s10</td>
</tr>
<tr>
<td class="label">To</td>
<td>uart_memory_u1/u_uart_txd/tx_flag_0_s8</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>865</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.226</td>
<td>0.244</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R12C10[0][A]</td>
<td>picorv32_core/uart_debug_u1/reset_out_s10/CLK</td>
</tr>
<tr>
<td>1.684</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>248</td>
<td>R12C10[0][A]</td>
<td style=" font-weight:bold;">picorv32_core/uart_debug_u1/reset_out_s10/Q</td>
</tr>
<tr>
<td>4.815</td>
<td>3.131</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R24C6[1][B]</td>
<td style=" font-weight:bold;">uart_memory_u1/u_uart_txd/tx_flag_0_s8/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>20.000</td>
<td>20.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>20.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>865</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>21.226</td>
<td>0.244</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R24C6[1][B]</td>
<td>uart_memory_u1/u_uart_txd/tx_flag_0_s8/CLK</td>
</tr>
<tr>
<td>21.182</td>
<td>-0.043</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R24C6[1][B]</td>
<td>uart_memory_u1/u_uart_txd/tx_flag_0_s8</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>20.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.982, 80.100%; route: 0.244, 19.900%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 3.131, 87.230%; tC2Q: 0.458, 12.770%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.982, 80.100%; route: 0.244, 19.900%</td>
</tr>
</table>
<h3>Path5</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>16.368</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>4.815</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>21.182</td>
</tr>
<tr>
<td class="label">From</td>
<td>picorv32_core/uart_debug_u1/reset_out_s10</td>
</tr>
<tr>
<td class="label">To</td>
<td>uart_memory_u1/u_uart_txd/uart_txd_0_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>865</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.226</td>
<td>0.244</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R12C10[0][A]</td>
<td>picorv32_core/uart_debug_u1/reset_out_s10/CLK</td>
</tr>
<tr>
<td>1.684</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>248</td>
<td>R12C10[0][A]</td>
<td style=" font-weight:bold;">picorv32_core/uart_debug_u1/reset_out_s10/Q</td>
</tr>
<tr>
<td>4.815</td>
<td>3.131</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>IOB2[A]</td>
<td style=" font-weight:bold;">uart_memory_u1/u_uart_txd/uart_txd_0_s1/PRESET</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>20.000</td>
<td>20.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>20.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>865</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>21.226</td>
<td>0.244</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>IOB2[A]</td>
<td>uart_memory_u1/u_uart_txd/uart_txd_0_s1/CLK</td>
</tr>
<tr>
<td>21.182</td>
<td>-0.043</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>IOB2[A]</td>
<td>uart_memory_u1/u_uart_txd/uart_txd_0_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>20.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.982, 80.100%; route: 0.244, 19.900%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 3.131, 87.230%; tC2Q: 0.458, 12.770%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.982, 80.100%; route: 0.244, 19.900%</td>
</tr>
</table>
<h3>Path6</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>16.368</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>4.815</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>21.182</td>
</tr>
<tr>
<td class="label">From</td>
<td>picorv32_core/uart_debug_u1/reset_out_s10</td>
</tr>
<tr>
<td class="label">To</td>
<td>uart_memory_u1/u_uart_txd/state_2_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>865</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.226</td>
<td>0.244</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R12C10[0][A]</td>
<td>picorv32_core/uart_debug_u1/reset_out_s10/CLK</td>
</tr>
<tr>
<td>1.684</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>248</td>
<td>R12C10[0][A]</td>
<td style=" font-weight:bold;">picorv32_core/uart_debug_u1/reset_out_s10/Q</td>
</tr>
<tr>
<td>4.815</td>
<td>3.131</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R24C6[2][A]</td>
<td style=" font-weight:bold;">uart_memory_u1/u_uart_txd/state_2_s1/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>20.000</td>
<td>20.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>20.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>865</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>21.226</td>
<td>0.244</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R24C6[2][A]</td>
<td>uart_memory_u1/u_uart_txd/state_2_s1/CLK</td>
</tr>
<tr>
<td>21.182</td>
<td>-0.043</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R24C6[2][A]</td>
<td>uart_memory_u1/u_uart_txd/state_2_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>20.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.982, 80.100%; route: 0.244, 19.900%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 3.131, 87.230%; tC2Q: 0.458, 12.770%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.982, 80.100%; route: 0.244, 19.900%</td>
</tr>
</table>
<h3>Path7</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>16.368</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>4.815</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>21.182</td>
</tr>
<tr>
<td class="label">From</td>
<td>picorv32_core/uart_debug_u1/reset_out_s10</td>
</tr>
<tr>
<td class="label">To</td>
<td>uart_memory_u1/u_uart_txd/uart_data_0_0_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>865</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.226</td>
<td>0.244</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R12C10[0][A]</td>
<td>picorv32_core/uart_debug_u1/reset_out_s10/CLK</td>
</tr>
<tr>
<td>1.684</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>248</td>
<td>R12C10[0][A]</td>
<td style=" font-weight:bold;">picorv32_core/uart_debug_u1/reset_out_s10/Q</td>
</tr>
<tr>
<td>4.815</td>
<td>3.131</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R24C8[1][A]</td>
<td style=" font-weight:bold;">uart_memory_u1/u_uart_txd/uart_data_0_0_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>20.000</td>
<td>20.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>20.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>865</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>21.226</td>
<td>0.244</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R24C8[1][A]</td>
<td>uart_memory_u1/u_uart_txd/uart_data_0_0_s0/CLK</td>
</tr>
<tr>
<td>21.182</td>
<td>-0.043</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R24C8[1][A]</td>
<td>uart_memory_u1/u_uart_txd/uart_data_0_0_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>20.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.982, 80.100%; route: 0.244, 19.900%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 3.131, 87.230%; tC2Q: 0.458, 12.770%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.982, 80.100%; route: 0.244, 19.900%</td>
</tr>
</table>
<h3>Path8</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>16.368</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>4.815</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>21.182</td>
</tr>
<tr>
<td class="label">From</td>
<td>picorv32_core/uart_debug_u1/reset_out_s10</td>
</tr>
<tr>
<td class="label">To</td>
<td>uart_memory_u1/u_uart_txd/cnt_clk_0_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>865</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.226</td>
<td>0.244</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R12C10[0][A]</td>
<td>picorv32_core/uart_debug_u1/reset_out_s10/CLK</td>
</tr>
<tr>
<td>1.684</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>248</td>
<td>R12C10[0][A]</td>
<td style=" font-weight:bold;">picorv32_core/uart_debug_u1/reset_out_s10/Q</td>
</tr>
<tr>
<td>4.815</td>
<td>3.131</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R24C7[2][B]</td>
<td style=" font-weight:bold;">uart_memory_u1/u_uart_txd/cnt_clk_0_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>20.000</td>
<td>20.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>20.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>865</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>21.226</td>
<td>0.244</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R24C7[2][B]</td>
<td>uart_memory_u1/u_uart_txd/cnt_clk_0_s0/CLK</td>
</tr>
<tr>
<td>21.182</td>
<td>-0.043</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R24C7[2][B]</td>
<td>uart_memory_u1/u_uart_txd/cnt_clk_0_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>20.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.982, 80.100%; route: 0.244, 19.900%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 3.131, 87.230%; tC2Q: 0.458, 12.770%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.982, 80.100%; route: 0.244, 19.900%</td>
</tr>
</table>
<h3>Path9</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>16.368</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>4.815</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>21.182</td>
</tr>
<tr>
<td class="label">From</td>
<td>picorv32_core/uart_debug_u1/reset_out_s10</td>
</tr>
<tr>
<td class="label">To</td>
<td>uart_memory_u1/u_uart_txd/cnt_clk_1_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>865</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.226</td>
<td>0.244</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R12C10[0][A]</td>
<td>picorv32_core/uart_debug_u1/reset_out_s10/CLK</td>
</tr>
<tr>
<td>1.684</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>248</td>
<td>R12C10[0][A]</td>
<td style=" font-weight:bold;">picorv32_core/uart_debug_u1/reset_out_s10/Q</td>
</tr>
<tr>
<td>4.815</td>
<td>3.131</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R23C6[2][A]</td>
<td style=" font-weight:bold;">uart_memory_u1/u_uart_txd/cnt_clk_1_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>20.000</td>
<td>20.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>20.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>865</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>21.226</td>
<td>0.244</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R23C6[2][A]</td>
<td>uart_memory_u1/u_uart_txd/cnt_clk_1_s0/CLK</td>
</tr>
<tr>
<td>21.182</td>
<td>-0.043</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R23C6[2][A]</td>
<td>uart_memory_u1/u_uart_txd/cnt_clk_1_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>20.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.982, 80.100%; route: 0.244, 19.900%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 3.131, 87.230%; tC2Q: 0.458, 12.770%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.982, 80.100%; route: 0.244, 19.900%</td>
</tr>
</table>
<h3>Path10</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>16.368</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>4.815</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>21.182</td>
</tr>
<tr>
<td class="label">From</td>
<td>picorv32_core/uart_debug_u1/reset_out_s10</td>
</tr>
<tr>
<td class="label">To</td>
<td>uart_memory_u1/u_uart_txd/cnt_clk_2_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>865</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.226</td>
<td>0.244</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R12C10[0][A]</td>
<td>picorv32_core/uart_debug_u1/reset_out_s10/CLK</td>
</tr>
<tr>
<td>1.684</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>248</td>
<td>R12C10[0][A]</td>
<td style=" font-weight:bold;">picorv32_core/uart_debug_u1/reset_out_s10/Q</td>
</tr>
<tr>
<td>4.815</td>
<td>3.131</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R23C6[1][A]</td>
<td style=" font-weight:bold;">uart_memory_u1/u_uart_txd/cnt_clk_2_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>20.000</td>
<td>20.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>20.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>865</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>21.226</td>
<td>0.244</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R23C6[1][A]</td>
<td>uart_memory_u1/u_uart_txd/cnt_clk_2_s0/CLK</td>
</tr>
<tr>
<td>21.182</td>
<td>-0.043</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R23C6[1][A]</td>
<td>uart_memory_u1/u_uart_txd/cnt_clk_2_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>20.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.982, 80.100%; route: 0.244, 19.900%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 3.131, 87.230%; tC2Q: 0.458, 12.770%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.982, 80.100%; route: 0.244, 19.900%</td>
</tr>
</table>
<h3>Path11</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>16.368</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>4.815</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>21.182</td>
</tr>
<tr>
<td class="label">From</td>
<td>picorv32_core/uart_debug_u1/reset_out_s10</td>
</tr>
<tr>
<td class="label">To</td>
<td>uart_memory_u1/u_uart_txd/cnt_clk_3_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>865</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.226</td>
<td>0.244</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R12C10[0][A]</td>
<td>picorv32_core/uart_debug_u1/reset_out_s10/CLK</td>
</tr>
<tr>
<td>1.684</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>248</td>
<td>R12C10[0][A]</td>
<td style=" font-weight:bold;">picorv32_core/uart_debug_u1/reset_out_s10/Q</td>
</tr>
<tr>
<td>4.815</td>
<td>3.131</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R23C6[0][B]</td>
<td style=" font-weight:bold;">uart_memory_u1/u_uart_txd/cnt_clk_3_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>20.000</td>
<td>20.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>20.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>865</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>21.226</td>
<td>0.244</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R23C6[0][B]</td>
<td>uart_memory_u1/u_uart_txd/cnt_clk_3_s0/CLK</td>
</tr>
<tr>
<td>21.182</td>
<td>-0.043</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R23C6[0][B]</td>
<td>uart_memory_u1/u_uart_txd/cnt_clk_3_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>20.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.982, 80.100%; route: 0.244, 19.900%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 3.131, 87.230%; tC2Q: 0.458, 12.770%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.982, 80.100%; route: 0.244, 19.900%</td>
</tr>
</table>
<h3>Path12</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>16.368</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>4.815</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>21.182</td>
</tr>
<tr>
<td class="label">From</td>
<td>picorv32_core/uart_debug_u1/reset_out_s10</td>
</tr>
<tr>
<td class="label">To</td>
<td>uart_memory_u1/u_uart_txd/cnt_clk_4_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>865</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.226</td>
<td>0.244</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R12C10[0][A]</td>
<td>picorv32_core/uart_debug_u1/reset_out_s10/CLK</td>
</tr>
<tr>
<td>1.684</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>248</td>
<td>R12C10[0][A]</td>
<td style=" font-weight:bold;">picorv32_core/uart_debug_u1/reset_out_s10/Q</td>
</tr>
<tr>
<td>4.815</td>
<td>3.131</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R24C6[0][A]</td>
<td style=" font-weight:bold;">uart_memory_u1/u_uart_txd/cnt_clk_4_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>20.000</td>
<td>20.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>20.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>865</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>21.226</td>
<td>0.244</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R24C6[0][A]</td>
<td>uart_memory_u1/u_uart_txd/cnt_clk_4_s0/CLK</td>
</tr>
<tr>
<td>21.182</td>
<td>-0.043</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R24C6[0][A]</td>
<td>uart_memory_u1/u_uart_txd/cnt_clk_4_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>20.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.982, 80.100%; route: 0.244, 19.900%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 3.131, 87.230%; tC2Q: 0.458, 12.770%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.982, 80.100%; route: 0.244, 19.900%</td>
</tr>
</table>
<h3>Path13</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>16.368</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>4.815</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>21.182</td>
</tr>
<tr>
<td class="label">From</td>
<td>picorv32_core/uart_debug_u1/reset_out_s10</td>
</tr>
<tr>
<td class="label">To</td>
<td>uart_memory_u1/u_uart_txd/uart_data_1_0_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>865</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.226</td>
<td>0.244</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R12C10[0][A]</td>
<td>picorv32_core/uart_debug_u1/reset_out_s10/CLK</td>
</tr>
<tr>
<td>1.684</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>248</td>
<td>R12C10[0][A]</td>
<td style=" font-weight:bold;">picorv32_core/uart_debug_u1/reset_out_s10/Q</td>
</tr>
<tr>
<td>4.815</td>
<td>3.131</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R22C6[0][A]</td>
<td style=" font-weight:bold;">uart_memory_u1/u_uart_txd/uart_data_1_0_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>20.000</td>
<td>20.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>20.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>865</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>21.226</td>
<td>0.244</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R22C6[0][A]</td>
<td>uart_memory_u1/u_uart_txd/uart_data_1_0_s0/CLK</td>
</tr>
<tr>
<td>21.182</td>
<td>-0.043</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R22C6[0][A]</td>
<td>uart_memory_u1/u_uart_txd/uart_data_1_0_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>20.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.982, 80.100%; route: 0.244, 19.900%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 3.131, 87.230%; tC2Q: 0.458, 12.770%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.982, 80.100%; route: 0.244, 19.900%</td>
</tr>
</table>
<h3>Path14</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>16.368</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>4.815</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>21.182</td>
</tr>
<tr>
<td class="label">From</td>
<td>picorv32_core/uart_debug_u1/reset_out_s10</td>
</tr>
<tr>
<td class="label">To</td>
<td>uart_memory_u1/u_uart_recv/state_1_s3</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>865</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.226</td>
<td>0.244</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R12C10[0][A]</td>
<td>picorv32_core/uart_debug_u1/reset_out_s10/CLK</td>
</tr>
<tr>
<td>1.684</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>248</td>
<td>R12C10[0][A]</td>
<td style=" font-weight:bold;">picorv32_core/uart_debug_u1/reset_out_s10/Q</td>
</tr>
<tr>
<td>4.815</td>
<td>3.131</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R24C11[1][A]</td>
<td style=" font-weight:bold;">uart_memory_u1/u_uart_recv/state_1_s3/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>20.000</td>
<td>20.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>20.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>865</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>21.226</td>
<td>0.244</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R24C11[1][A]</td>
<td>uart_memory_u1/u_uart_recv/state_1_s3/CLK</td>
</tr>
<tr>
<td>21.182</td>
<td>-0.043</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R24C11[1][A]</td>
<td>uart_memory_u1/u_uart_recv/state_1_s3</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>20.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.982, 80.100%; route: 0.244, 19.900%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 3.131, 87.230%; tC2Q: 0.458, 12.770%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.982, 80.100%; route: 0.244, 19.900%</td>
</tr>
</table>
<h3>Path15</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>16.368</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>4.815</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>21.182</td>
</tr>
<tr>
<td class="label">From</td>
<td>picorv32_core/uart_debug_u1/reset_out_s10</td>
</tr>
<tr>
<td class="label">To</td>
<td>uart_memory_u1/u_uart_recv/state_3_s10</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>865</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.226</td>
<td>0.244</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R12C10[0][A]</td>
<td>picorv32_core/uart_debug_u1/reset_out_s10/CLK</td>
</tr>
<tr>
<td>1.684</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>248</td>
<td>R12C10[0][A]</td>
<td style=" font-weight:bold;">picorv32_core/uart_debug_u1/reset_out_s10/Q</td>
</tr>
<tr>
<td>4.815</td>
<td>3.131</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R24C11[0][B]</td>
<td style=" font-weight:bold;">uart_memory_u1/u_uart_recv/state_3_s10/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>20.000</td>
<td>20.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>20.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>865</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>21.226</td>
<td>0.244</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R24C11[0][B]</td>
<td>uart_memory_u1/u_uart_recv/state_3_s10/CLK</td>
</tr>
<tr>
<td>21.182</td>
<td>-0.043</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R24C11[0][B]</td>
<td>uart_memory_u1/u_uart_recv/state_3_s10</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>20.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.982, 80.100%; route: 0.244, 19.900%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 3.131, 87.230%; tC2Q: 0.458, 12.770%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.982, 80.100%; route: 0.244, 19.900%</td>
</tr>
</table>
<h3>Path16</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>16.368</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>4.815</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>21.182</td>
</tr>
<tr>
<td class="label">From</td>
<td>picorv32_core/uart_debug_u1/reset_out_s10</td>
</tr>
<tr>
<td class="label">To</td>
<td>uart_memory_u1/u_uart_recv/state_0_s3</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>865</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.226</td>
<td>0.244</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R12C10[0][A]</td>
<td>picorv32_core/uart_debug_u1/reset_out_s10/CLK</td>
</tr>
<tr>
<td>1.684</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>248</td>
<td>R12C10[0][A]</td>
<td style=" font-weight:bold;">picorv32_core/uart_debug_u1/reset_out_s10/Q</td>
</tr>
<tr>
<td>4.815</td>
<td>3.131</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R22C8[0][A]</td>
<td style=" font-weight:bold;">uart_memory_u1/u_uart_recv/state_0_s3/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>20.000</td>
<td>20.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>20.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>865</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>21.226</td>
<td>0.244</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R22C8[0][A]</td>
<td>uart_memory_u1/u_uart_recv/state_0_s3/CLK</td>
</tr>
<tr>
<td>21.182</td>
<td>-0.043</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R22C8[0][A]</td>
<td>uart_memory_u1/u_uart_recv/state_0_s3</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>20.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.982, 80.100%; route: 0.244, 19.900%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 3.131, 87.230%; tC2Q: 0.458, 12.770%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.982, 80.100%; route: 0.244, 19.900%</td>
</tr>
</table>
<h3>Path17</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>16.368</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>4.815</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>21.182</td>
</tr>
<tr>
<td class="label">From</td>
<td>picorv32_core/uart_debug_u1/reset_out_s10</td>
</tr>
<tr>
<td class="label">To</td>
<td>uart_memory_u1/u_uart_recv/uart_data_0_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>865</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.226</td>
<td>0.244</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R12C10[0][A]</td>
<td>picorv32_core/uart_debug_u1/reset_out_s10/CLK</td>
</tr>
<tr>
<td>1.684</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>248</td>
<td>R12C10[0][A]</td>
<td style=" font-weight:bold;">picorv32_core/uart_debug_u1/reset_out_s10/Q</td>
</tr>
<tr>
<td>4.815</td>
<td>3.131</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C8[2][B]</td>
<td style=" font-weight:bold;">uart_memory_u1/u_uart_recv/uart_data_0_s1/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>20.000</td>
<td>20.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>20.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>865</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>21.226</td>
<td>0.244</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C8[2][B]</td>
<td>uart_memory_u1/u_uart_recv/uart_data_0_s1/CLK</td>
</tr>
<tr>
<td>21.182</td>
<td>-0.043</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R18C8[2][B]</td>
<td>uart_memory_u1/u_uart_recv/uart_data_0_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>20.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.982, 80.100%; route: 0.244, 19.900%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 3.131, 87.230%; tC2Q: 0.458, 12.770%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.982, 80.100%; route: 0.244, 19.900%</td>
</tr>
</table>
<h3>Path18</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>16.368</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>4.815</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>21.182</td>
</tr>
<tr>
<td class="label">From</td>
<td>picorv32_core/uart_debug_u1/reset_out_s10</td>
</tr>
<tr>
<td class="label">To</td>
<td>uart_memory_u1/u_uart_recv/uart_data_1_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>865</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.226</td>
<td>0.244</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R12C10[0][A]</td>
<td>picorv32_core/uart_debug_u1/reset_out_s10/CLK</td>
</tr>
<tr>
<td>1.684</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>248</td>
<td>R12C10[0][A]</td>
<td style=" font-weight:bold;">picorv32_core/uart_debug_u1/reset_out_s10/Q</td>
</tr>
<tr>
<td>4.815</td>
<td>3.131</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C8[2][A]</td>
<td style=" font-weight:bold;">uart_memory_u1/u_uart_recv/uart_data_1_s1/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>20.000</td>
<td>20.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>20.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>865</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>21.226</td>
<td>0.244</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C8[2][A]</td>
<td>uart_memory_u1/u_uart_recv/uart_data_1_s1/CLK</td>
</tr>
<tr>
<td>21.182</td>
<td>-0.043</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R18C8[2][A]</td>
<td>uart_memory_u1/u_uart_recv/uart_data_1_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>20.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.982, 80.100%; route: 0.244, 19.900%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 3.131, 87.230%; tC2Q: 0.458, 12.770%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.982, 80.100%; route: 0.244, 19.900%</td>
</tr>
</table>
<h3>Path19</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>16.368</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>4.815</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>21.182</td>
</tr>
<tr>
<td class="label">From</td>
<td>picorv32_core/uart_debug_u1/reset_out_s10</td>
</tr>
<tr>
<td class="label">To</td>
<td>uart_memory_u1/u_uart_recv/uart_data_2_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>865</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.226</td>
<td>0.244</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R12C10[0][A]</td>
<td>picorv32_core/uart_debug_u1/reset_out_s10/CLK</td>
</tr>
<tr>
<td>1.684</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>248</td>
<td>R12C10[0][A]</td>
<td style=" font-weight:bold;">picorv32_core/uart_debug_u1/reset_out_s10/Q</td>
</tr>
<tr>
<td>4.815</td>
<td>3.131</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C8[1][B]</td>
<td style=" font-weight:bold;">uart_memory_u1/u_uart_recv/uart_data_2_s1/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>20.000</td>
<td>20.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>20.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>865</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>21.226</td>
<td>0.244</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C8[1][B]</td>
<td>uart_memory_u1/u_uart_recv/uart_data_2_s1/CLK</td>
</tr>
<tr>
<td>21.182</td>
<td>-0.043</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R18C8[1][B]</td>
<td>uart_memory_u1/u_uart_recv/uart_data_2_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>20.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.982, 80.100%; route: 0.244, 19.900%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 3.131, 87.230%; tC2Q: 0.458, 12.770%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.982, 80.100%; route: 0.244, 19.900%</td>
</tr>
</table>
<h3>Path20</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>16.368</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>4.815</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>21.182</td>
</tr>
<tr>
<td class="label">From</td>
<td>picorv32_core/uart_debug_u1/reset_out_s10</td>
</tr>
<tr>
<td class="label">To</td>
<td>uart_memory_u1/u_uart_recv/uart_data_3_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>865</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.226</td>
<td>0.244</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R12C10[0][A]</td>
<td>picorv32_core/uart_debug_u1/reset_out_s10/CLK</td>
</tr>
<tr>
<td>1.684</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>248</td>
<td>R12C10[0][A]</td>
<td style=" font-weight:bold;">picorv32_core/uart_debug_u1/reset_out_s10/Q</td>
</tr>
<tr>
<td>4.815</td>
<td>3.131</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C8[1][A]</td>
<td style=" font-weight:bold;">uart_memory_u1/u_uart_recv/uart_data_3_s1/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>20.000</td>
<td>20.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>20.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>865</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>21.226</td>
<td>0.244</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C8[1][A]</td>
<td>uart_memory_u1/u_uart_recv/uart_data_3_s1/CLK</td>
</tr>
<tr>
<td>21.182</td>
<td>-0.043</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R18C8[1][A]</td>
<td>uart_memory_u1/u_uart_recv/uart_data_3_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>20.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.982, 80.100%; route: 0.244, 19.900%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 3.131, 87.230%; tC2Q: 0.458, 12.770%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.982, 80.100%; route: 0.244, 19.900%</td>
</tr>
</table>
<h3>Path21</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>16.368</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>4.815</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>21.182</td>
</tr>
<tr>
<td class="label">From</td>
<td>picorv32_core/uart_debug_u1/reset_out_s10</td>
</tr>
<tr>
<td class="label">To</td>
<td>uart_memory_u1/u_uart_recv/uart_data_4_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>865</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.226</td>
<td>0.244</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R12C10[0][A]</td>
<td>picorv32_core/uart_debug_u1/reset_out_s10/CLK</td>
</tr>
<tr>
<td>1.684</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>248</td>
<td>R12C10[0][A]</td>
<td style=" font-weight:bold;">picorv32_core/uart_debug_u1/reset_out_s10/Q</td>
</tr>
<tr>
<td>4.815</td>
<td>3.131</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C8[0][B]</td>
<td style=" font-weight:bold;">uart_memory_u1/u_uart_recv/uart_data_4_s1/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>20.000</td>
<td>20.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>20.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>865</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>21.226</td>
<td>0.244</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C8[0][B]</td>
<td>uart_memory_u1/u_uart_recv/uart_data_4_s1/CLK</td>
</tr>
<tr>
<td>21.182</td>
<td>-0.043</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R18C8[0][B]</td>
<td>uart_memory_u1/u_uart_recv/uart_data_4_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>20.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.982, 80.100%; route: 0.244, 19.900%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 3.131, 87.230%; tC2Q: 0.458, 12.770%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.982, 80.100%; route: 0.244, 19.900%</td>
</tr>
</table>
<h3>Path22</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>16.368</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>4.815</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>21.182</td>
</tr>
<tr>
<td class="label">From</td>
<td>picorv32_core/uart_debug_u1/reset_out_s10</td>
</tr>
<tr>
<td class="label">To</td>
<td>uart_memory_u1/u_uart_recv/uart_data_5_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>865</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.226</td>
<td>0.244</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R12C10[0][A]</td>
<td>picorv32_core/uart_debug_u1/reset_out_s10/CLK</td>
</tr>
<tr>
<td>1.684</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>248</td>
<td>R12C10[0][A]</td>
<td style=" font-weight:bold;">picorv32_core/uart_debug_u1/reset_out_s10/Q</td>
</tr>
<tr>
<td>4.815</td>
<td>3.131</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C8[0][A]</td>
<td style=" font-weight:bold;">uart_memory_u1/u_uart_recv/uart_data_5_s1/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>20.000</td>
<td>20.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>20.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>865</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>21.226</td>
<td>0.244</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C8[0][A]</td>
<td>uart_memory_u1/u_uart_recv/uart_data_5_s1/CLK</td>
</tr>
<tr>
<td>21.182</td>
<td>-0.043</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R18C8[0][A]</td>
<td>uart_memory_u1/u_uart_recv/uart_data_5_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>20.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.982, 80.100%; route: 0.244, 19.900%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 3.131, 87.230%; tC2Q: 0.458, 12.770%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.982, 80.100%; route: 0.244, 19.900%</td>
</tr>
</table>
<h3>Path23</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>16.368</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>4.815</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>21.182</td>
</tr>
<tr>
<td class="label">From</td>
<td>picorv32_core/uart_debug_u1/reset_out_s10</td>
</tr>
<tr>
<td class="label">To</td>
<td>uart_memory_u1/u_uart_recv/uart_data_6_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>865</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.226</td>
<td>0.244</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R12C10[0][A]</td>
<td>picorv32_core/uart_debug_u1/reset_out_s10/CLK</td>
</tr>
<tr>
<td>1.684</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>248</td>
<td>R12C10[0][A]</td>
<td style=" font-weight:bold;">picorv32_core/uart_debug_u1/reset_out_s10/Q</td>
</tr>
<tr>
<td>4.815</td>
<td>3.131</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R23C11[0][B]</td>
<td style=" font-weight:bold;">uart_memory_u1/u_uart_recv/uart_data_6_s1/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>20.000</td>
<td>20.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>20.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>865</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>21.226</td>
<td>0.244</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R23C11[0][B]</td>
<td>uart_memory_u1/u_uart_recv/uart_data_6_s1/CLK</td>
</tr>
<tr>
<td>21.182</td>
<td>-0.043</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R23C11[0][B]</td>
<td>uart_memory_u1/u_uart_recv/uart_data_6_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>20.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.982, 80.100%; route: 0.244, 19.900%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 3.131, 87.230%; tC2Q: 0.458, 12.770%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.982, 80.100%; route: 0.244, 19.900%</td>
</tr>
</table>
<h3>Path24</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>16.368</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>4.815</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>21.182</td>
</tr>
<tr>
<td class="label">From</td>
<td>picorv32_core/uart_debug_u1/reset_out_s10</td>
</tr>
<tr>
<td class="label">To</td>
<td>uart_memory_u1/u_uart_recv/uart_data_7_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>865</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.226</td>
<td>0.244</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R12C10[0][A]</td>
<td>picorv32_core/uart_debug_u1/reset_out_s10/CLK</td>
</tr>
<tr>
<td>1.684</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>248</td>
<td>R12C10[0][A]</td>
<td style=" font-weight:bold;">picorv32_core/uart_debug_u1/reset_out_s10/Q</td>
</tr>
<tr>
<td>4.815</td>
<td>3.131</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R23C11[0][A]</td>
<td style=" font-weight:bold;">uart_memory_u1/u_uart_recv/uart_data_7_s1/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>20.000</td>
<td>20.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>20.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>865</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>21.226</td>
<td>0.244</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R23C11[0][A]</td>
<td>uart_memory_u1/u_uart_recv/uart_data_7_s1/CLK</td>
</tr>
<tr>
<td>21.182</td>
<td>-0.043</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R23C11[0][A]</td>
<td>uart_memory_u1/u_uart_recv/uart_data_7_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>20.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.982, 80.100%; route: 0.244, 19.900%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 3.131, 87.230%; tC2Q: 0.458, 12.770%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.982, 80.100%; route: 0.244, 19.900%</td>
</tr>
</table>
<h3>Path25</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>16.368</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>4.815</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>21.182</td>
</tr>
<tr>
<td class="label">From</td>
<td>picorv32_core/uart_debug_u1/reset_out_s10</td>
</tr>
<tr>
<td class="label">To</td>
<td>uart_memory_u1/u_uart_recv/state_2_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>865</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.226</td>
<td>0.244</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R12C10[0][A]</td>
<td>picorv32_core/uart_debug_u1/reset_out_s10/CLK</td>
</tr>
<tr>
<td>1.684</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>248</td>
<td>R12C10[0][A]</td>
<td style=" font-weight:bold;">picorv32_core/uart_debug_u1/reset_out_s10/Q</td>
</tr>
<tr>
<td>4.815</td>
<td>3.131</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R22C8[1][A]</td>
<td style=" font-weight:bold;">uart_memory_u1/u_uart_recv/state_2_s1/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>20.000</td>
<td>20.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>20.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>865</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>21.226</td>
<td>0.244</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R22C8[1][A]</td>
<td>uart_memory_u1/u_uart_recv/state_2_s1/CLK</td>
</tr>
<tr>
<td>21.182</td>
<td>-0.043</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R22C8[1][A]</td>
<td>uart_memory_u1/u_uart_recv/state_2_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>20.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.982, 80.100%; route: 0.244, 19.900%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 3.131, 87.230%; tC2Q: 0.458, 12.770%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.982, 80.100%; route: 0.244, 19.900%</td>
</tr>
</table>
<h3><a name="Removal_Analysis">Removal Analysis Report</a></h3>
<h4>Report Command:report_timing -removal -max_paths 25 -max_common_paths 1</h4>
<h3>Path1</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.895</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.939</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.044</td>
</tr>
<tr>
<td class="label">From</td>
<td>uart_memory_u1/overtime_oe_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>uart_memory_u1/overtime_0_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>865</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.029</td>
<td>0.185</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C7[1][A]</td>
<td>uart_memory_u1/overtime_oe_s0/CLK</td>
</tr>
<tr>
<td>1.362</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>30</td>
<td>R21C7[1][A]</td>
<td style=" font-weight:bold;">uart_memory_u1/overtime_oe_s0/Q</td>
</tr>
<tr>
<td>1.939</td>
<td>0.577</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C5[2][B]</td>
<td style=" font-weight:bold;">uart_memory_u1/overtime_0_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>865</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.029</td>
<td>0.185</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C5[2][B]</td>
<td>uart_memory_u1/overtime_0_s0/CLK</td>
</tr>
<tr>
<td>1.044</td>
<td>0.015</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R20C5[2][B]</td>
<td>uart_memory_u1/overtime_0_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.844, 82.061%; route: 0.185, 17.939%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.577, 63.366%; tC2Q: 0.333, 36.634%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.844, 82.061%; route: 0.185, 17.939%</td>
</tr>
</table>
<h3>Path2</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.901</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.945</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.044</td>
</tr>
<tr>
<td class="label">From</td>
<td>uart_memory_u1/overtime_oe_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>uart_memory_u1/overtime_6_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>865</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.029</td>
<td>0.185</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C7[1][A]</td>
<td>uart_memory_u1/overtime_oe_s0/CLK</td>
</tr>
<tr>
<td>1.362</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>30</td>
<td>R21C7[1][A]</td>
<td style=" font-weight:bold;">uart_memory_u1/overtime_oe_s0/Q</td>
</tr>
<tr>
<td>1.945</td>
<td>0.583</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C7[0][A]</td>
<td style=" font-weight:bold;">uart_memory_u1/overtime_6_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>865</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.029</td>
<td>0.185</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C7[0][A]</td>
<td>uart_memory_u1/overtime_6_s0/CLK</td>
</tr>
<tr>
<td>1.044</td>
<td>0.015</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R20C7[0][A]</td>
<td>uart_memory_u1/overtime_6_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.844, 82.061%; route: 0.185, 17.939%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.583, 63.608%; tC2Q: 0.333, 36.392%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.844, 82.061%; route: 0.185, 17.939%</td>
</tr>
</table>
<h3>Path3</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.901</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.945</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.044</td>
</tr>
<tr>
<td class="label">From</td>
<td>uart_memory_u1/overtime_oe_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>uart_memory_u1/overtime_7_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>865</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.029</td>
<td>0.185</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C7[1][A]</td>
<td>uart_memory_u1/overtime_oe_s0/CLK</td>
</tr>
<tr>
<td>1.362</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>30</td>
<td>R21C7[1][A]</td>
<td style=" font-weight:bold;">uart_memory_u1/overtime_oe_s0/Q</td>
</tr>
<tr>
<td>1.945</td>
<td>0.583</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C7[0][B]</td>
<td style=" font-weight:bold;">uart_memory_u1/overtime_7_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>865</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.029</td>
<td>0.185</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C7[0][B]</td>
<td>uart_memory_u1/overtime_7_s0/CLK</td>
</tr>
<tr>
<td>1.044</td>
<td>0.015</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R20C7[0][B]</td>
<td>uart_memory_u1/overtime_7_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.844, 82.061%; route: 0.185, 17.939%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.583, 63.608%; tC2Q: 0.333, 36.392%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.844, 82.061%; route: 0.185, 17.939%</td>
</tr>
</table>
<h3>Path4</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.901</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.945</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.044</td>
</tr>
<tr>
<td class="label">From</td>
<td>uart_memory_u1/overtime_oe_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>uart_memory_u1/overtime_8_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>865</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.029</td>
<td>0.185</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C7[1][A]</td>
<td>uart_memory_u1/overtime_oe_s0/CLK</td>
</tr>
<tr>
<td>1.362</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>30</td>
<td>R21C7[1][A]</td>
<td style=" font-weight:bold;">uart_memory_u1/overtime_oe_s0/Q</td>
</tr>
<tr>
<td>1.945</td>
<td>0.583</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C7[1][A]</td>
<td style=" font-weight:bold;">uart_memory_u1/overtime_8_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>865</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.029</td>
<td>0.185</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C7[1][A]</td>
<td>uart_memory_u1/overtime_8_s0/CLK</td>
</tr>
<tr>
<td>1.044</td>
<td>0.015</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R20C7[1][A]</td>
<td>uart_memory_u1/overtime_8_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.844, 82.061%; route: 0.185, 17.939%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.583, 63.608%; tC2Q: 0.333, 36.392%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.844, 82.061%; route: 0.185, 17.939%</td>
</tr>
</table>
<h3>Path5</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.901</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.945</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.044</td>
</tr>
<tr>
<td class="label">From</td>
<td>uart_memory_u1/overtime_oe_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>uart_memory_u1/overtime_9_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>865</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.029</td>
<td>0.185</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C7[1][A]</td>
<td>uart_memory_u1/overtime_oe_s0/CLK</td>
</tr>
<tr>
<td>1.362</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>30</td>
<td>R21C7[1][A]</td>
<td style=" font-weight:bold;">uart_memory_u1/overtime_oe_s0/Q</td>
</tr>
<tr>
<td>1.945</td>
<td>0.583</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C7[1][B]</td>
<td style=" font-weight:bold;">uart_memory_u1/overtime_9_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>865</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.029</td>
<td>0.185</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C7[1][B]</td>
<td>uart_memory_u1/overtime_9_s0/CLK</td>
</tr>
<tr>
<td>1.044</td>
<td>0.015</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R20C7[1][B]</td>
<td>uart_memory_u1/overtime_9_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.844, 82.061%; route: 0.185, 17.939%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.583, 63.608%; tC2Q: 0.333, 36.392%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.844, 82.061%; route: 0.185, 17.939%</td>
</tr>
</table>
<h3>Path6</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.901</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.945</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.044</td>
</tr>
<tr>
<td class="label">From</td>
<td>uart_memory_u1/overtime_oe_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>uart_memory_u1/overtime_10_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>865</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.029</td>
<td>0.185</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C7[1][A]</td>
<td>uart_memory_u1/overtime_oe_s0/CLK</td>
</tr>
<tr>
<td>1.362</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>30</td>
<td>R21C7[1][A]</td>
<td style=" font-weight:bold;">uart_memory_u1/overtime_oe_s0/Q</td>
</tr>
<tr>
<td>1.945</td>
<td>0.583</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C7[2][A]</td>
<td style=" font-weight:bold;">uart_memory_u1/overtime_10_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>865</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.029</td>
<td>0.185</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C7[2][A]</td>
<td>uart_memory_u1/overtime_10_s0/CLK</td>
</tr>
<tr>
<td>1.044</td>
<td>0.015</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R20C7[2][A]</td>
<td>uart_memory_u1/overtime_10_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.844, 82.061%; route: 0.185, 17.939%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.583, 63.608%; tC2Q: 0.333, 36.392%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.844, 82.061%; route: 0.185, 17.939%</td>
</tr>
</table>
<h3>Path7</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.901</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.945</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.044</td>
</tr>
<tr>
<td class="label">From</td>
<td>uart_memory_u1/overtime_oe_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>uart_memory_u1/overtime_11_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>865</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.029</td>
<td>0.185</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C7[1][A]</td>
<td>uart_memory_u1/overtime_oe_s0/CLK</td>
</tr>
<tr>
<td>1.362</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>30</td>
<td>R21C7[1][A]</td>
<td style=" font-weight:bold;">uart_memory_u1/overtime_oe_s0/Q</td>
</tr>
<tr>
<td>1.945</td>
<td>0.583</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C7[2][B]</td>
<td style=" font-weight:bold;">uart_memory_u1/overtime_11_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>865</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.029</td>
<td>0.185</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C7[2][B]</td>
<td>uart_memory_u1/overtime_11_s0/CLK</td>
</tr>
<tr>
<td>1.044</td>
<td>0.015</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R20C7[2][B]</td>
<td>uart_memory_u1/overtime_11_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.844, 82.061%; route: 0.185, 17.939%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.583, 63.608%; tC2Q: 0.333, 36.392%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.844, 82.061%; route: 0.185, 17.939%</td>
</tr>
</table>
<h3>Path8</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.902</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.946</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.044</td>
</tr>
<tr>
<td class="label">From</td>
<td>uart_memory_u1/overtime_oe_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>uart_memory_u1/overtime_1_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>865</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.029</td>
<td>0.185</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C7[1][A]</td>
<td>uart_memory_u1/overtime_oe_s0/CLK</td>
</tr>
<tr>
<td>1.362</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>30</td>
<td>R21C7[1][A]</td>
<td style=" font-weight:bold;">uart_memory_u1/overtime_oe_s0/Q</td>
</tr>
<tr>
<td>1.946</td>
<td>0.584</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C6[0][B]</td>
<td style=" font-weight:bold;">uart_memory_u1/overtime_1_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>865</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.029</td>
<td>0.185</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C6[0][B]</td>
<td>uart_memory_u1/overtime_1_s0/CLK</td>
</tr>
<tr>
<td>1.044</td>
<td>0.015</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R20C6[0][B]</td>
<td>uart_memory_u1/overtime_1_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.844, 82.061%; route: 0.185, 17.939%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.584, 63.666%; tC2Q: 0.333, 36.334%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.844, 82.061%; route: 0.185, 17.939%</td>
</tr>
</table>
<h3>Path9</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.902</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.946</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.044</td>
</tr>
<tr>
<td class="label">From</td>
<td>uart_memory_u1/overtime_oe_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>uart_memory_u1/overtime_2_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>865</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.029</td>
<td>0.185</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C7[1][A]</td>
<td>uart_memory_u1/overtime_oe_s0/CLK</td>
</tr>
<tr>
<td>1.362</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>30</td>
<td>R21C7[1][A]</td>
<td style=" font-weight:bold;">uart_memory_u1/overtime_oe_s0/Q</td>
</tr>
<tr>
<td>1.946</td>
<td>0.584</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C6[1][A]</td>
<td style=" font-weight:bold;">uart_memory_u1/overtime_2_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>865</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.029</td>
<td>0.185</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C6[1][A]</td>
<td>uart_memory_u1/overtime_2_s0/CLK</td>
</tr>
<tr>
<td>1.044</td>
<td>0.015</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R20C6[1][A]</td>
<td>uart_memory_u1/overtime_2_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.844, 82.061%; route: 0.185, 17.939%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.584, 63.666%; tC2Q: 0.333, 36.334%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.844, 82.061%; route: 0.185, 17.939%</td>
</tr>
</table>
<h3>Path10</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.902</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.946</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.044</td>
</tr>
<tr>
<td class="label">From</td>
<td>uart_memory_u1/overtime_oe_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>uart_memory_u1/overtime_3_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>865</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.029</td>
<td>0.185</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C7[1][A]</td>
<td>uart_memory_u1/overtime_oe_s0/CLK</td>
</tr>
<tr>
<td>1.362</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>30</td>
<td>R21C7[1][A]</td>
<td style=" font-weight:bold;">uart_memory_u1/overtime_oe_s0/Q</td>
</tr>
<tr>
<td>1.946</td>
<td>0.584</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C6[1][B]</td>
<td style=" font-weight:bold;">uart_memory_u1/overtime_3_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>865</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.029</td>
<td>0.185</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C6[1][B]</td>
<td>uart_memory_u1/overtime_3_s0/CLK</td>
</tr>
<tr>
<td>1.044</td>
<td>0.015</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R20C6[1][B]</td>
<td>uart_memory_u1/overtime_3_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.844, 82.061%; route: 0.185, 17.939%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.584, 63.666%; tC2Q: 0.333, 36.334%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.844, 82.061%; route: 0.185, 17.939%</td>
</tr>
</table>
<h3>Path11</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.902</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.946</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.044</td>
</tr>
<tr>
<td class="label">From</td>
<td>uart_memory_u1/overtime_oe_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>uart_memory_u1/overtime_4_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>865</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.029</td>
<td>0.185</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C7[1][A]</td>
<td>uart_memory_u1/overtime_oe_s0/CLK</td>
</tr>
<tr>
<td>1.362</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>30</td>
<td>R21C7[1][A]</td>
<td style=" font-weight:bold;">uart_memory_u1/overtime_oe_s0/Q</td>
</tr>
<tr>
<td>1.946</td>
<td>0.584</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C6[2][A]</td>
<td style=" font-weight:bold;">uart_memory_u1/overtime_4_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>865</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.029</td>
<td>0.185</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C6[2][A]</td>
<td>uart_memory_u1/overtime_4_s0/CLK</td>
</tr>
<tr>
<td>1.044</td>
<td>0.015</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R20C6[2][A]</td>
<td>uart_memory_u1/overtime_4_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.844, 82.061%; route: 0.185, 17.939%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.584, 63.666%; tC2Q: 0.333, 36.334%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.844, 82.061%; route: 0.185, 17.939%</td>
</tr>
</table>
<h3>Path12</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.902</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.946</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.044</td>
</tr>
<tr>
<td class="label">From</td>
<td>uart_memory_u1/overtime_oe_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>uart_memory_u1/overtime_5_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>865</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.029</td>
<td>0.185</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C7[1][A]</td>
<td>uart_memory_u1/overtime_oe_s0/CLK</td>
</tr>
<tr>
<td>1.362</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>30</td>
<td>R21C7[1][A]</td>
<td style=" font-weight:bold;">uart_memory_u1/overtime_oe_s0/Q</td>
</tr>
<tr>
<td>1.946</td>
<td>0.584</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C6[2][B]</td>
<td style=" font-weight:bold;">uart_memory_u1/overtime_5_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>865</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.029</td>
<td>0.185</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C6[2][B]</td>
<td>uart_memory_u1/overtime_5_s0/CLK</td>
</tr>
<tr>
<td>1.044</td>
<td>0.015</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R20C6[2][B]</td>
<td>uart_memory_u1/overtime_5_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.844, 82.061%; route: 0.185, 17.939%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.584, 63.666%; tC2Q: 0.333, 36.334%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.844, 82.061%; route: 0.185, 17.939%</td>
</tr>
</table>
<h3>Path13</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.902</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.946</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.044</td>
</tr>
<tr>
<td class="label">From</td>
<td>uart_memory_u1/overtime_oe_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>uart_memory_u1/overtime_12_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>865</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.029</td>
<td>0.185</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C7[1][A]</td>
<td>uart_memory_u1/overtime_oe_s0/CLK</td>
</tr>
<tr>
<td>1.362</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>30</td>
<td>R21C7[1][A]</td>
<td style=" font-weight:bold;">uart_memory_u1/overtime_oe_s0/Q</td>
</tr>
<tr>
<td>1.946</td>
<td>0.584</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C8[0][A]</td>
<td style=" font-weight:bold;">uart_memory_u1/overtime_12_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>865</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.029</td>
<td>0.185</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C8[0][A]</td>
<td>uart_memory_u1/overtime_12_s0/CLK</td>
</tr>
<tr>
<td>1.044</td>
<td>0.015</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R20C8[0][A]</td>
<td>uart_memory_u1/overtime_12_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.844, 82.061%; route: 0.185, 17.939%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.584, 63.666%; tC2Q: 0.333, 36.334%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.844, 82.061%; route: 0.185, 17.939%</td>
</tr>
</table>
<h3>Path14</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.902</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.946</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.044</td>
</tr>
<tr>
<td class="label">From</td>
<td>uart_memory_u1/overtime_oe_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>uart_memory_u1/overtime_13_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>865</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.029</td>
<td>0.185</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C7[1][A]</td>
<td>uart_memory_u1/overtime_oe_s0/CLK</td>
</tr>
<tr>
<td>1.362</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>30</td>
<td>R21C7[1][A]</td>
<td style=" font-weight:bold;">uart_memory_u1/overtime_oe_s0/Q</td>
</tr>
<tr>
<td>1.946</td>
<td>0.584</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C8[0][B]</td>
<td style=" font-weight:bold;">uart_memory_u1/overtime_13_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>865</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.029</td>
<td>0.185</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C8[0][B]</td>
<td>uart_memory_u1/overtime_13_s0/CLK</td>
</tr>
<tr>
<td>1.044</td>
<td>0.015</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R20C8[0][B]</td>
<td>uart_memory_u1/overtime_13_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.844, 82.061%; route: 0.185, 17.939%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.584, 63.666%; tC2Q: 0.333, 36.334%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.844, 82.061%; route: 0.185, 17.939%</td>
</tr>
</table>
<h3>Path15</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.902</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.946</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.044</td>
</tr>
<tr>
<td class="label">From</td>
<td>uart_memory_u1/overtime_oe_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>uart_memory_u1/overtime_14_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>865</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.029</td>
<td>0.185</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C7[1][A]</td>
<td>uart_memory_u1/overtime_oe_s0/CLK</td>
</tr>
<tr>
<td>1.362</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>30</td>
<td>R21C7[1][A]</td>
<td style=" font-weight:bold;">uart_memory_u1/overtime_oe_s0/Q</td>
</tr>
<tr>
<td>1.946</td>
<td>0.584</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C8[1][A]</td>
<td style=" font-weight:bold;">uart_memory_u1/overtime_14_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>865</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.029</td>
<td>0.185</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C8[1][A]</td>
<td>uart_memory_u1/overtime_14_s0/CLK</td>
</tr>
<tr>
<td>1.044</td>
<td>0.015</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R20C8[1][A]</td>
<td>uart_memory_u1/overtime_14_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.844, 82.061%; route: 0.185, 17.939%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.584, 63.666%; tC2Q: 0.333, 36.334%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.844, 82.061%; route: 0.185, 17.939%</td>
</tr>
</table>
<h3>Path16</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.902</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.946</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.044</td>
</tr>
<tr>
<td class="label">From</td>
<td>uart_memory_u1/overtime_oe_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>uart_memory_u1/overtime_15_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>865</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.029</td>
<td>0.185</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C7[1][A]</td>
<td>uart_memory_u1/overtime_oe_s0/CLK</td>
</tr>
<tr>
<td>1.362</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>30</td>
<td>R21C7[1][A]</td>
<td style=" font-weight:bold;">uart_memory_u1/overtime_oe_s0/Q</td>
</tr>
<tr>
<td>1.946</td>
<td>0.584</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C8[1][B]</td>
<td style=" font-weight:bold;">uart_memory_u1/overtime_15_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>865</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.029</td>
<td>0.185</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C8[1][B]</td>
<td>uart_memory_u1/overtime_15_s0/CLK</td>
</tr>
<tr>
<td>1.044</td>
<td>0.015</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R20C8[1][B]</td>
<td>uart_memory_u1/overtime_15_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.844, 82.061%; route: 0.185, 17.939%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.584, 63.666%; tC2Q: 0.333, 36.334%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.844, 82.061%; route: 0.185, 17.939%</td>
</tr>
</table>
<h3>Path17</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.902</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.946</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.044</td>
</tr>
<tr>
<td class="label">From</td>
<td>uart_memory_u1/overtime_oe_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>uart_memory_u1/overtime_16_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>865</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.029</td>
<td>0.185</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C7[1][A]</td>
<td>uart_memory_u1/overtime_oe_s0/CLK</td>
</tr>
<tr>
<td>1.362</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>30</td>
<td>R21C7[1][A]</td>
<td style=" font-weight:bold;">uart_memory_u1/overtime_oe_s0/Q</td>
</tr>
<tr>
<td>1.946</td>
<td>0.584</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C8[2][A]</td>
<td style=" font-weight:bold;">uart_memory_u1/overtime_16_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>865</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.029</td>
<td>0.185</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C8[2][A]</td>
<td>uart_memory_u1/overtime_16_s0/CLK</td>
</tr>
<tr>
<td>1.044</td>
<td>0.015</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R20C8[2][A]</td>
<td>uart_memory_u1/overtime_16_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.844, 82.061%; route: 0.185, 17.939%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.584, 63.666%; tC2Q: 0.333, 36.334%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.844, 82.061%; route: 0.185, 17.939%</td>
</tr>
</table>
<h3>Path18</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.902</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.946</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.044</td>
</tr>
<tr>
<td class="label">From</td>
<td>uart_memory_u1/overtime_oe_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>uart_memory_u1/overtime_17_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>865</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.029</td>
<td>0.185</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C7[1][A]</td>
<td>uart_memory_u1/overtime_oe_s0/CLK</td>
</tr>
<tr>
<td>1.362</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>30</td>
<td>R21C7[1][A]</td>
<td style=" font-weight:bold;">uart_memory_u1/overtime_oe_s0/Q</td>
</tr>
<tr>
<td>1.946</td>
<td>0.584</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C8[2][B]</td>
<td style=" font-weight:bold;">uart_memory_u1/overtime_17_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>865</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.029</td>
<td>0.185</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C8[2][B]</td>
<td>uart_memory_u1/overtime_17_s0/CLK</td>
</tr>
<tr>
<td>1.044</td>
<td>0.015</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R20C8[2][B]</td>
<td>uart_memory_u1/overtime_17_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.844, 82.061%; route: 0.185, 17.939%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.584, 63.666%; tC2Q: 0.333, 36.334%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.844, 82.061%; route: 0.185, 17.939%</td>
</tr>
</table>
<h3>Path19</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.902</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.946</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.044</td>
</tr>
<tr>
<td class="label">From</td>
<td>uart_memory_u1/overtime_oe_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>uart_memory_u1/overtime_18_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>865</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.029</td>
<td>0.185</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C7[1][A]</td>
<td>uart_memory_u1/overtime_oe_s0/CLK</td>
</tr>
<tr>
<td>1.362</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>30</td>
<td>R21C7[1][A]</td>
<td style=" font-weight:bold;">uart_memory_u1/overtime_oe_s0/Q</td>
</tr>
<tr>
<td>1.946</td>
<td>0.584</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C9[0][A]</td>
<td style=" font-weight:bold;">uart_memory_u1/overtime_18_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>865</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.029</td>
<td>0.185</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C9[0][A]</td>
<td>uart_memory_u1/overtime_18_s0/CLK</td>
</tr>
<tr>
<td>1.044</td>
<td>0.015</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R20C9[0][A]</td>
<td>uart_memory_u1/overtime_18_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.844, 82.061%; route: 0.185, 17.939%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.584, 63.666%; tC2Q: 0.333, 36.334%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.844, 82.061%; route: 0.185, 17.939%</td>
</tr>
</table>
<h3>Path20</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.902</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.946</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.044</td>
</tr>
<tr>
<td class="label">From</td>
<td>uart_memory_u1/overtime_oe_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>uart_memory_u1/overtime_19_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>865</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.029</td>
<td>0.185</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C7[1][A]</td>
<td>uart_memory_u1/overtime_oe_s0/CLK</td>
</tr>
<tr>
<td>1.362</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>30</td>
<td>R21C7[1][A]</td>
<td style=" font-weight:bold;">uart_memory_u1/overtime_oe_s0/Q</td>
</tr>
<tr>
<td>1.946</td>
<td>0.584</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C9[0][B]</td>
<td style=" font-weight:bold;">uart_memory_u1/overtime_19_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>865</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.029</td>
<td>0.185</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C9[0][B]</td>
<td>uart_memory_u1/overtime_19_s0/CLK</td>
</tr>
<tr>
<td>1.044</td>
<td>0.015</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R20C9[0][B]</td>
<td>uart_memory_u1/overtime_19_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.844, 82.061%; route: 0.185, 17.939%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.584, 63.666%; tC2Q: 0.333, 36.334%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.844, 82.061%; route: 0.185, 17.939%</td>
</tr>
</table>
<h3>Path21</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.902</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.946</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.044</td>
</tr>
<tr>
<td class="label">From</td>
<td>uart_memory_u1/overtime_oe_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>uart_memory_u1/overtime_20_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>865</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.029</td>
<td>0.185</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C7[1][A]</td>
<td>uart_memory_u1/overtime_oe_s0/CLK</td>
</tr>
<tr>
<td>1.362</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>30</td>
<td>R21C7[1][A]</td>
<td style=" font-weight:bold;">uart_memory_u1/overtime_oe_s0/Q</td>
</tr>
<tr>
<td>1.946</td>
<td>0.584</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C9[1][A]</td>
<td style=" font-weight:bold;">uart_memory_u1/overtime_20_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>865</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.029</td>
<td>0.185</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C9[1][A]</td>
<td>uart_memory_u1/overtime_20_s0/CLK</td>
</tr>
<tr>
<td>1.044</td>
<td>0.015</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R20C9[1][A]</td>
<td>uart_memory_u1/overtime_20_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.844, 82.061%; route: 0.185, 17.939%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.584, 63.666%; tC2Q: 0.333, 36.334%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.844, 82.061%; route: 0.185, 17.939%</td>
</tr>
</table>
<h3>Path22</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.902</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.946</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.044</td>
</tr>
<tr>
<td class="label">From</td>
<td>uart_memory_u1/overtime_oe_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>uart_memory_u1/overtime_21_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>865</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.029</td>
<td>0.185</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C7[1][A]</td>
<td>uart_memory_u1/overtime_oe_s0/CLK</td>
</tr>
<tr>
<td>1.362</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>30</td>
<td>R21C7[1][A]</td>
<td style=" font-weight:bold;">uart_memory_u1/overtime_oe_s0/Q</td>
</tr>
<tr>
<td>1.946</td>
<td>0.584</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C9[1][B]</td>
<td style=" font-weight:bold;">uart_memory_u1/overtime_21_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>865</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.029</td>
<td>0.185</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C9[1][B]</td>
<td>uart_memory_u1/overtime_21_s0/CLK</td>
</tr>
<tr>
<td>1.044</td>
<td>0.015</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R20C9[1][B]</td>
<td>uart_memory_u1/overtime_21_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.844, 82.061%; route: 0.185, 17.939%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.584, 63.666%; tC2Q: 0.333, 36.334%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.844, 82.061%; route: 0.185, 17.939%</td>
</tr>
</table>
<h3>Path23</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.902</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.946</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.044</td>
</tr>
<tr>
<td class="label">From</td>
<td>uart_memory_u1/overtime_oe_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>uart_memory_u1/overtime_22_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>865</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.029</td>
<td>0.185</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C7[1][A]</td>
<td>uart_memory_u1/overtime_oe_s0/CLK</td>
</tr>
<tr>
<td>1.362</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>30</td>
<td>R21C7[1][A]</td>
<td style=" font-weight:bold;">uart_memory_u1/overtime_oe_s0/Q</td>
</tr>
<tr>
<td>1.946</td>
<td>0.584</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C9[2][A]</td>
<td style=" font-weight:bold;">uart_memory_u1/overtime_22_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>865</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.029</td>
<td>0.185</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C9[2][A]</td>
<td>uart_memory_u1/overtime_22_s0/CLK</td>
</tr>
<tr>
<td>1.044</td>
<td>0.015</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R20C9[2][A]</td>
<td>uart_memory_u1/overtime_22_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.844, 82.061%; route: 0.185, 17.939%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.584, 63.666%; tC2Q: 0.333, 36.334%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.844, 82.061%; route: 0.185, 17.939%</td>
</tr>
</table>
<h3>Path24</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.902</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.946</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.044</td>
</tr>
<tr>
<td class="label">From</td>
<td>uart_memory_u1/overtime_oe_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>uart_memory_u1/overtime_23_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>865</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.029</td>
<td>0.185</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C7[1][A]</td>
<td>uart_memory_u1/overtime_oe_s0/CLK</td>
</tr>
<tr>
<td>1.362</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>30</td>
<td>R21C7[1][A]</td>
<td style=" font-weight:bold;">uart_memory_u1/overtime_oe_s0/Q</td>
</tr>
<tr>
<td>1.946</td>
<td>0.584</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C9[2][B]</td>
<td style=" font-weight:bold;">uart_memory_u1/overtime_23_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>865</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.029</td>
<td>0.185</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C9[2][B]</td>
<td>uart_memory_u1/overtime_23_s0/CLK</td>
</tr>
<tr>
<td>1.044</td>
<td>0.015</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R20C9[2][B]</td>
<td>uart_memory_u1/overtime_23_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.844, 82.061%; route: 0.185, 17.939%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.584, 63.666%; tC2Q: 0.333, 36.334%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.844, 82.061%; route: 0.185, 17.939%</td>
</tr>
</table>
<h3>Path25</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>1.161</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>2.205</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.044</td>
</tr>
<tr>
<td class="label">From</td>
<td>uart_memory_u1/overtime_oe_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>uart_memory_u1/overtime_24_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>865</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.029</td>
<td>0.185</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C7[1][A]</td>
<td>uart_memory_u1/overtime_oe_s0/CLK</td>
</tr>
<tr>
<td>1.362</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>30</td>
<td>R21C7[1][A]</td>
<td style=" font-weight:bold;">uart_memory_u1/overtime_oe_s0/Q</td>
</tr>
<tr>
<td>2.205</td>
<td>0.843</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C10[0][A]</td>
<td style=" font-weight:bold;">uart_memory_u1/overtime_24_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>865</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.029</td>
<td>0.185</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C10[0][A]</td>
<td>uart_memory_u1/overtime_24_s0/CLK</td>
</tr>
<tr>
<td>1.044</td>
<td>0.015</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R20C10[0][A]</td>
<td>uart_memory_u1/overtime_24_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.844, 82.061%; route: 0.185, 17.939%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.843, 71.654%; tC2Q: 0.333, 28.346%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.844, 82.061%; route: 0.185, 17.939%</td>
</tr>
</table>
<h2><a name="Minimum_Pulse_Width_Report">Minimum Pulse Width Report:</a></h2>
<h4>Report Command:report_min_pulse_width -nworst 10 -detail</h4>
<h3>MPW1</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>8.532</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>9.782</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>1.250</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>Low Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>clk</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>out_byte_7_s2</td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>10.984</td>
<td>0.984</td>
<td>tINS</td>
<td>FF</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>11.247</td>
<td>0.262</td>
<td>tNET</td>
<td>FF</td>
<td>out_byte_7_s2/CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>20.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>21.029</td>
<td>0.185</td>
<td>tNET</td>
<td>RR</td>
<td>out_byte_7_s2/CLK</td>
</tr>
</table>
<h3>MPW2</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>8.532</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>9.782</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>1.250</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>Low Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>clk</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>out_byte_5_s1</td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>10.984</td>
<td>0.984</td>
<td>tINS</td>
<td>FF</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>11.247</td>
<td>0.262</td>
<td>tNET</td>
<td>FF</td>
<td>out_byte_5_s1/CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>20.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>21.029</td>
<td>0.185</td>
<td>tNET</td>
<td>RR</td>
<td>out_byte_5_s1/CLK</td>
</tr>
</table>
<h3>MPW3</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>8.532</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>9.782</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>1.250</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>Low Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>clk</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>out_byte_1_s1</td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>10.984</td>
<td>0.984</td>
<td>tINS</td>
<td>FF</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>11.247</td>
<td>0.262</td>
<td>tNET</td>
<td>FF</td>
<td>out_byte_1_s1/CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>20.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>21.029</td>
<td>0.185</td>
<td>tNET</td>
<td>RR</td>
<td>out_byte_1_s1/CLK</td>
</tr>
</table>
<h3>MPW4</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>8.532</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>9.782</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>1.250</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>Low Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>clk</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>mem_rdata_r0_25_s0</td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>10.984</td>
<td>0.984</td>
<td>tINS</td>
<td>FF</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>11.247</td>
<td>0.262</td>
<td>tNET</td>
<td>FF</td>
<td>mem_rdata_r0_25_s0/CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>20.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>21.029</td>
<td>0.185</td>
<td>tNET</td>
<td>RR</td>
<td>mem_rdata_r0_25_s0/CLK</td>
</tr>
</table>
<h3>MPW5</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>8.532</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>9.782</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>1.250</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>Low Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>clk</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>mem_rdata_r0_9_s0</td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>10.984</td>
<td>0.984</td>
<td>tINS</td>
<td>FF</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>11.247</td>
<td>0.262</td>
<td>tNET</td>
<td>FF</td>
<td>mem_rdata_r0_9_s0/CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>20.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>21.029</td>
<td>0.185</td>
<td>tNET</td>
<td>RR</td>
<td>mem_rdata_r0_9_s0/CLK</td>
</tr>
</table>
<h3>MPW6</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>8.532</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>9.782</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>1.250</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>Low Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>clk</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>picorv32_core/timer_cnt_12_s0</td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>10.984</td>
<td>0.984</td>
<td>tINS</td>
<td>FF</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>11.247</td>
<td>0.262</td>
<td>tNET</td>
<td>FF</td>
<td>picorv32_core/timer_cnt_12_s0/CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>20.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>21.029</td>
<td>0.185</td>
<td>tNET</td>
<td>RR</td>
<td>picorv32_core/timer_cnt_12_s0/CLK</td>
</tr>
</table>
<h3>MPW7</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>8.532</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>9.782</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>1.250</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>Low Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>clk</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>picorv32_core/pcpi_rd_12_s0</td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>10.984</td>
<td>0.984</td>
<td>tINS</td>
<td>FF</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>11.247</td>
<td>0.262</td>
<td>tNET</td>
<td>FF</td>
<td>picorv32_core/pcpi_rd_12_s0/CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>20.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>21.029</td>
<td>0.185</td>
<td>tNET</td>
<td>RR</td>
<td>picorv32_core/pcpi_rd_12_s0/CLK</td>
</tr>
</table>
<h3>MPW8</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>8.532</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>9.782</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>1.250</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>Low Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>clk</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>picorv32_core/riscv32_alu_u1/irq_reg_15_s0</td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>10.984</td>
<td>0.984</td>
<td>tINS</td>
<td>FF</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>11.247</td>
<td>0.262</td>
<td>tNET</td>
<td>FF</td>
<td>picorv32_core/riscv32_alu_u1/irq_reg_15_s0/CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>20.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>21.029</td>
<td>0.185</td>
<td>tNET</td>
<td>RR</td>
<td>picorv32_core/riscv32_alu_u1/irq_reg_15_s0/CLK</td>
</tr>
</table>
<h3>MPW9</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>8.532</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>9.782</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>1.250</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>Low Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>clk</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>picorv32_core/riscv32_alu_u1/op2num_17_s0</td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>10.984</td>
<td>0.984</td>
<td>tINS</td>
<td>FF</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>11.247</td>
<td>0.262</td>
<td>tNET</td>
<td>FF</td>
<td>picorv32_core/riscv32_alu_u1/op2num_17_s0/CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>20.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>21.029</td>
<td>0.185</td>
<td>tNET</td>
<td>RR</td>
<td>picorv32_core/riscv32_alu_u1/op2num_17_s0/CLK</td>
</tr>
</table>
<h3>MPW10</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>8.532</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>9.782</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>1.250</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>Low Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>clk</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>picorv32_core/riscv32_alu_u1/op2num_18_s0</td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>10.984</td>
<td>0.984</td>
<td>tINS</td>
<td>FF</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>11.247</td>
<td>0.262</td>
<td>tNET</td>
<td>FF</td>
<td>picorv32_core/riscv32_alu_u1/op2num_18_s0/CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>20.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>21.029</td>
<td>0.185</td>
<td>tNET</td>
<td>RR</td>
<td>picorv32_core/riscv32_alu_u1/op2num_18_s0/CLK</td>
</tr>
</table>
<h2><a name="High_Fanout_Nets_Report">High Fanout Nets Report:</a></h2>
<h4>Report Command:report_high_fanout_nets -max_nets 10</h4>
<table class="detail_table">
<tr>
<th class="label">FANOUT</th>
<th class="label">NET NAME</th>
<th class="label">WORST SLACK</th>
<th class="label">MAX DELAY</th>
</tr>
<tr>
<td>865</td>
<td>clk_d</td>
<td>-0.642</td>
<td>0.262</td>
</tr>
<tr>
<td>248</td>
<td>cpu_reset</td>
<td>7.051</td>
<td>3.946</td>
</tr>
<tr>
<td>189</td>
<td>n2405_12</td>
<td>2.612</td>
<td>4.164</td>
</tr>
<tr>
<td>186</td>
<td>reg_rdata_7_8</td>
<td>3.554</td>
<td>3.079</td>
</tr>
<tr>
<td>160</td>
<td>instruction_reg[12]</td>
<td>0.998</td>
<td>3.637</td>
</tr>
<tr>
<td>124</td>
<td>instruction_reg[13]</td>
<td>0.378</td>
<td>3.481</td>
</tr>
<tr>
<td>123</td>
<td>op2num[3]</td>
<td>0.915</td>
<td>2.956</td>
</tr>
<tr>
<td>113</td>
<td>instruction_reg[14]</td>
<td>-0.246</td>
<td>3.037</td>
</tr>
<tr>
<td>99</td>
<td>op2num[2]</td>
<td>0.702</td>
<td>2.631</td>
</tr>
<tr>
<td>92</td>
<td>cpu_state[0]</td>
<td>4.915</td>
<td>3.311</td>
</tr>
</table>
<h2><a name="Route_Congestions_Report">Route Congestions Report:</a></h2>
<h4>Report Command:report_route_congestion -max_grids 10</h4>
<table class="detail_table">
<tr>
<th class="label">GRID LOC</th>
<th class="label">ROUTE CONGESTIONS</th>
</tr>
<tr>
<td>R15C27</td>
<td>93.06%</td>
</tr>
<tr>
<td>R16C25</td>
<td>93.06%</td>
</tr>
<tr>
<td>R14C24</td>
<td>91.67%</td>
</tr>
<tr>
<td>R17C31</td>
<td>91.67%</td>
</tr>
<tr>
<td>R12C34</td>
<td>90.28%</td>
</tr>
<tr>
<td>R15C28</td>
<td>90.28%</td>
</tr>
<tr>
<td>R15C23</td>
<td>88.89%</td>
</tr>
<tr>
<td>R15C24</td>
<td>88.89%</td>
</tr>
<tr>
<td>R12C29</td>
<td>88.89%</td>
</tr>
<tr>
<td>R18C28</td>
<td>88.89%</td>
</tr>
</table>
<h2><a name="Timing_Exceptions_Report">Timing Exceptions Report:</a></h2>
<h3><a name="Setup_Analysis_Exceptions">Setup Analysis Report</a></h3>
<h4>Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1</h4>
<h4>No timing exceptions to report!</h4>
<h3><a name="Hold_Analysis_Exceptions">Hold Analysis Report</a></h3>
<h4>Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1</h4>
<h4>No timing exceptions to report!</h4>
<h3><a name="Recovery_Analysis_Exceptions">Recovery Analysis Report</a></h3>
<h4>Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1</h4>
<h4>No timing exceptions to report!</h4>
<h3><a name="Removal_Analysis_Exceptions">Removal Analysis Report</a></h3>
<h4>Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1</h4>
<h4>No timing exceptions to report!</h4>
<h2><a name="SDC_Report">Timing Constraints Report:</a></h2>
<table class="detail_table">
<tr>
<th class="label">SDC Command Type</th>
<th class="label">State</th>
<th class="label">Detail Command</th>
</tr>
</table>
</div><!-- content -->
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